SBOS771A December   2016  – January 2019 OPA4277-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions: CFP
    2.     Pin Functions: CDIP
    3. 5.1 Bare Die Information
      1.      Bond Pad Coordinates in Microns
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Protection
      2. 7.3.2 Input Bias Current Cancellation
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.1 Bare Die Information

DIE THICKNESS BACKSIDE FINISH BACKSIDE
POTENTIAL		 BOND PAD
METALLIZATION COMPOSITION		 BOND PAD
THICKNESS
15 mils Silicon with backgrind Negative (lower) Power Supply AlCu (0.5%) 990 to 1210 nm
OPA4277-SP Bondpad_graphic_newer_sbos771.png

Bond Pad Coordinates in Microns(1)

PAD I/O DESCRIPTION X MIN Y MIN X MAX Y MAX
NO. NAME
1 OUT A O Output channel A. 1791.042 7290.340 1901.751 7401.049
2 –IN A I Inverting input channel A. 1701.719 6111.536 1807.397 6217.213
3 +IN A I Noninverting input channel A. 1701.719 5326.505 1812.429 5437.215
4 V+ — Positive (higher) power supply. 1555.784 4390.507 1661.461 4498.700
5 +IN B I Noninverting input channel B. 1706.752 3462.057 1807.397 3562.702
6 –IN B I Inverting input channel B. 1701.719 2671.994 1807.397 2777.671
7 OUT B O Output channel B. 1796.074 1498.222 1896.719 1598.867
8 OUT C O Output channel C. 3278.071 1498.222 3383.748 1603.900
9 –IN C I Inverting input channel C. 3362.361 2671.994 3473.071 2782.704
10 +IN C I Noninverting input channel C. 3367.393 3462.057 3473.071 3567.734
11 V– — Negative (lower) power supply. 3407.651 4391.765 3513.329 4497.442
12 +IN D I Noninverting input channel D. 3367.393 5331.537 3468.038 5432.182
13 –IN D I Inverting input channel D. 3362.361 6111.536 3468.038 6217.213
14 OUT D O Output channel D. 3273.039 7290.340 3383.748 7401.049
(1) Substrate must be biased to V–, negative (lower) power supply.