SBAS703A June   2015  – June 2015 OPT9221

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DDR2 Interface
      2. 7.3.2 I2C Master Interface
      3. 7.3.3 Timing Coordinator
        1. 7.3.3.1 Basic Frame Structure
        2. 7.3.3.2 Frame Rate Control and Sub Frames
        3. 7.3.3.3 Input Clock Generation
        4. 7.3.3.4 Sensor Addressing Engine
          1. 7.3.3.4.1 Region of Interest (ROI)
          2. 7.3.3.4.2 Readout Sequence
        5. 7.3.3.5 Integration Time
          1. 7.3.3.5.1 High Dynamic Range Functionality
        6. 7.3.3.6 Modulation Clock Generator
          1. 7.3.3.6.1 Sensor Output Signals
      4. 7.3.4 Output Interface
        1. 7.3.4.1 Output Data Format
          1. 7.3.4.1.1 4-Byte Mode (default)
          2. 7.3.4.1.2 2-Byte Mode
          3. 7.3.4.1.3 Register Controls
        2. 7.3.4.2 Frame Fragmentation
        3. 7.3.4.3 Data Output Waveforms
          1. 7.3.4.3.1 8-Lane Mode - DVP
          2. 7.3.4.3.2 8-Lane Mode - Generic Parallel Interface
          3. 7.3.4.3.3 4-Lane Mode - SSI
          4. 7.3.4.3.4 1-Lane Mode - SSI
          5. 7.3.4.3.5 Register Controls
      5. 7.3.5 Modulation Frequency
      6. 7.3.6 LVDS Receiver and Deserializer
      7. 7.3.7 Depth Engine
        1. 7.3.7.1 Phase Data
        2. 7.3.7.2 De-Aliasing
          1. 7.3.7.2.1 Procedure for Enabling the De-Aliasing Mode
          2. 7.3.7.2.2 Procedure for Disabling the De-Aliasing Mode
          3. 7.3.7.2.3 Setting the De-Aliasing Coefficients
          4. 7.3.7.2.4 Scaling of Phase
          5. 7.3.7.2.5 LSBs in the De-Aliased Phase
        3. 7.3.7.3 Binning
        4. 7.3.7.4 Spatial Filter
        5. 7.3.7.5 Auxiliary Depth Data
      8. 7.3.8 Calibration
        1. 7.3.8.1 Phase Offset Correction
        2. 7.3.8.2 Illumination Path Delay Correction Using Feedback
        3. 7.3.8.3 Phase Non-Linearity Correction
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby and Low-Power Modes
    5. 7.5 Programming
      1. 7.5.1 Boot Sequence
        1. 7.5.1.1 Configuration
          1. 7.5.1.1.1 Master Serial Configuration
          2. 7.5.1.1.2 Slave Serial Configuration (SS mode)
          3. 7.5.1.1.3 Slave Parallel Configuration (SP mode)
          4. 7.5.1.1.4 Slave Parallel and Serial Timing
      2. 7.5.2 Slave I2C Interface
    6. 7.6 Register Maps
      1. 7.6.1 Serial Interface Register Map
      2. 7.6.2 Register Descriptions
        1. 7.6.2.1  Register 0h (offset = 0h) [reset = 0h]
        2. 7.6.2.2  Register 1h (offset = 1h) [reset = 1XXh]
        3. 7.6.2.3  Register 2h (offset = 2h) [reset = 100C81h]
        4. 7.6.2.4  Register 3h (offset = 3h) [reset = 100000h]
        5. 7.6.2.5  Register 4h (offset = 4h) [reset = 0h]
        6. 7.6.2.6  Register 5h (offset = 5h) [reset = 7FFFh]
        7. 7.6.2.7  Register 6h (offset = 6h) [reset = 0h]
        8. 7.6.2.8  Register 7h (offset = 7h) [reset = 8001h]
        9. 7.6.2.9  Register 8h (offset = 8h) [reset = 0h]
        10. 7.6.2.10 Register 9h (offset = 9h) [reset = 0h]
        11. 7.6.2.11 Register Ah (offset = Ah) [reset = 7FFFh]
        12. 7.6.2.12 Register Bh (offset = Bh) [reset = 0h]
        13. 7.6.2.13 Register Ch (offset = Ch) [reset = 8001h]
        14. 7.6.2.14 Register Dh (offset = Dh) [reset = 0h]
        15. 7.6.2.15 Register Eh (offset = Eh) [reset = 0h]
        16. 7.6.2.16 Register Fh (offset = Fh) [reset = 0h]
        17. 7.6.2.17 Register 10h (offset = 10h) [reset = 0h]
        18. 7.6.2.18 Register 11h (offset = 11h) [reset = 6ED9h]
        19. 7.6.2.19 Register 12h (offset = 12h) [reset = 9127h]
        20. 7.6.2.20 Register 13h (offset = 13h) [reset = 0h]
        21. 7.6.2.21 Register 14h (offset = 14h) [reset = 6ED9h]
        22. 7.6.2.22 Register 15h (offset = 15h) [reset = 9127h]
        23. 7.6.2.23 Register 16h (offset = 16h) [reset = 7FFFh]
        24. 7.6.2.24 Register 17h (offset = 17h) [reset = C000h]
        25. 7.6.2.25 Register 18h (offset = 18h) [reset = C000h]
        26. 7.6.2.26 Register 19h (offset = 19h) [reset = 7FFFh]
        27. 7.6.2.27 Register 1Ah (offset = 1Ah) [reset = C000h]
        28. 7.6.2.28 Register 1Bh (offset = 1Bh) [reset = C000h]
        29. 7.6.2.29 Register 1Fh (offset = 1Fh) [reset = 54321h]
        30. 7.6.2.30 Register 25h (offset = 25h) [reset = 80001h]
        31. 7.6.2.31 Register 27h (offset = 27h) [reset = 2000h]
        32. 7.6.2.32 Register 28h (offset = 28h) [reset = 0h]
        33. 7.6.2.33 Register 29h (offset = 29h) [reset = 304000h]
        34. 7.6.2.34 Register 2Eh (offset = 2Eh) [reset = 871h]
        35. 7.6.2.35 Register 2Fh (offset = 2Fh) [reset = 3C0001h]
        36. 7.6.2.36 Register 30h (offset = 30h) [reset = 500001h]
        37. 7.6.2.37 Register 31h (offset = 31h) [reset = 1802h]
        38. 7.6.2.38 Register 33h (offset = 33h) [reset = 30h]
        39. 7.6.2.39 Register 35h (offset = 35h) [reset = 800000h]
        40. 7.6.2.40 Register 36h (offset = 36h) [reset = 0h]
        41. 7.6.2.41 Register 37h (offset = 37h) [reset = 0h]
        42. 7.6.2.42 Register 38h (offset = 38h) [reset = 0h]
        43. 7.6.2.43 Register 39h (offset = 39h) [reset = 0h]
        44. 7.6.2.44 Register 3Ah (offset = 3Ah) [reset = 0h]
        45. 7.6.2.45 Register 3Bh (offset = 3Bh) [reset = 0h]
        46. 7.6.2.46 Register 3Ch (offset = 3Ch) [reset = 4000h]
        47. 7.6.2.47 Register 3Dh (offset = 3Dh) [reset = 0h]
        48. 7.6.2.48 Register 3Eh (offset = 3Eh) [reset = 80h]
        49. 7.6.2.49 Register 3Fh (offset = 3Fh) [reset = Bh]
        50. 7.6.2.50 Register 40h (offset = 40h) [reset = 50455h]
        51. 7.6.2.51 Register 47h (offset = 47h) [reset = 0h]
        52. 7.6.2.52 Register 48h (offset = 48h) [reset = 0h]
        53. 7.6.2.53 Register 4Ch (offset = 4Ch) [reset = 800006h]
        54. 7.6.2.54 Register 4Dh (offset = 4Dh) [reset = 0h]
        55. 7.6.2.55 Register 51h (offset = 51h) [reset = 140000h]
        56. 7.6.2.56 Register 52h (offset = 52h) [reset = 0h]
        57. 7.6.2.57 Register 61h (offset = 61h) [reset = 0h]
        58. 7.6.2.58 Register 62h (offset = 62h) [reset = 0h]
        59. 7.6.2.59 Register 63h (offset = 63h) [reset = 0h]
        60. 7.6.2.60 Register 65h (offset = 65h) [reset = 0h]
        61. 7.6.2.61 Register 66h (offset = 66h) [reset = 0h]
        62. 7.6.2.62 Register 80h (offset = 80h) [reset = 0h]
        63. 7.6.2.63 Register 81h (offset = 81h) [reset = 0h]
        64. 7.6.2.64 Register 82h (offset = 82h) [reset = 0h]
        65. 7.6.2.65 Register 83h (offset = 83h) [reset = 0h]
        66. 7.6.2.66 Register 84h (offset = 84h) [reset = 0h]
        67. 7.6.2.67 Register 85h (offset = 85h) [reset = 0h]
        68. 7.6.2.68 Register 86h (offset = 86h) [reset = 0h]
        69. 7.6.2.69 Register 87h (offset = 87h) [reset = 0h]
        70. 7.6.2.70 Register 88h (offset = 88h) [reset = 0h]
        71. 7.6.2.71 Register 91h (offset = 91h) [reset = 0h]
        72. 7.6.2.72 Register 92h (offset = 92h) [reset = 0h]
        73. 7.6.2.73 Register 93h (offset = 93h) [reset = 0h]
        74. 7.6.2.74 Register 94h (offset = 94h) [reset = 0h]
        75. 7.6.2.75 Register 95h (offset = 95h) [reset = 0h]
        76. 7.6.2.76 Register 96h (offset = 96h) [reset = 0h]
        77. 7.6.2.77 Register 97h (offset = 97h) [reset = 0h]
        78. 7.6.2.78 Register 98h (offset = 98h) [reset = 0h]
        79. 7.6.2.79 Register ABh (offset = ABh) [reset = 0h]
        80. 7.6.2.80 Register ACh (offset = ACh) [reset = 0h]
        81. 7.6.2.81 Register ADh (offset = ADh) [reset = 0h]
        82. 7.6.2.82 Register AEh (offset = AEh) [reset = 0h]
        83. 7.6.2.83 Register AFh (offset = AFh) [reset = 0h]
        84. 7.6.2.84 Register B0h (offset = B0h) [reset = 0h]
        85. 7.6.2.85 Register B1h (offset = B1h) [reset = 5004h]
        86. 7.6.2.86 Register B2h (offset = B2h) [reset = C00h]
        87. 7.6.2.87 Register B3h (offset = B3h) [reset = 800h]
        88. 7.6.2.88 Register B6h (offset = B6h) [reset = 0h]
      3. 7.6.3 Serial Interface Register Map
        1. 7.6.3.1  Register 2h (offset = 2h) [reset = 0h]
        2. 7.6.3.2  Register Ch (offset = Ch) [reset = 100000h]
        3. 7.6.3.3  Register Dh (offset = Dh) [reset = 100000h]
        4. 7.6.3.4  Register Eh (offset = Eh) [reset = 04h]
        5. 7.6.3.5  Register Fh (offset = Fh) [reset = 49Ah]
        6. 7.6.3.6  Register 12h (offset = 12h) [reset = 0h]
        7. 7.6.3.7  Register 1Fh (offset = 1Fh) [reset = EF0000h]
        8. 7.6.3.8  Register 20h (offset = 20h) [reset = 0h]
        9. 7.6.3.9  Register 21h (offset = 21h) [reset = 40009Fh]
        10. 7.6.3.10 Register 22h (offset = 22h) [reset = 12020h]
        11. 7.6.3.11 Register 80h (offset = 80h) [reset = 1h]
        12. 7.6.3.12 Register 81h (offset = 81h) [reset = A0h]
        13. 7.6.3.13 Register 82h (offset = 82h) [reset = 186A0h]
        14. 7.6.3.14 Register 83h (offset = 83h) [reset = 44h]
        15. 7.6.3.15 Register CCh (offset = CCh) [reset = 400003h]
        16. 7.6.3.16 Register D6h (offset = D6h) [reset = 1h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 DDR Placement and Routing
      2. 10.1.2 LVDS Receiver
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Power Supply Recommendations

9.1 Power-Up Sequence

The power rails VCCA, VCCIO, VCCD_PLL, and VCC_INT can come up in any order.  All the rails have to rise monotonically to the recommended voltage levels within tRAMP time (see Figure 16). A power on reset (POR) is internally generated as soon as all the power rails are within the recommended levels.