SCPS141J September   2006  – March 2021 PCA9534A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description (Continued)
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Resistance Characteristics
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Device Functional Modes
      1. 9.2.1 Power-On Reset
      2. 9.2.2 I/O Port
      3. 9.2.3 Interrupt Output ( INT)
        1. 9.2.3.1 Interrupt Errata
          1. 9.2.3.1.1 Description
          2. 9.2.3.1.2 System Impact
          3. 9.2.3.1.3 System Workaround
    3. 9.3 Programming
      1. 9.3.1 I2C Interface
      2. 9.3.2 Register Map
        1. 9.3.2.1 Device Address
        2. 9.3.2.2 Control Register And Command Byte
        3. 9.3.2.3 Register Descriptions
        4. 9.3.2.4 Bus Transactions
          1. 9.3.2.4.1 Writes
          2. 9.3.2.4.2 Reads
  10. 10Application Information Disclaimer
    1. 10.1 Application Information
      1. 10.1.1 Typical Application
        1. 10.1.1.1 Design Requirements
          1. 10.1.1.1.1 Minimizing ICC When The I/O Controls Leds
  11. 11Power Supply Recommendations
    1. 11.1 Power-On Reset Requirements
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.2.1 Device Address

Figure 9-6 shows the address byte of the PCA9534A.

GUID-B03D1996-B0D2-42C2-AEC3-852ED01D7192-low.gifFigure 9-6 Pca9534a Address
Table 9-2 Address Reference
INPUTSI2C BUS SLAVE ADDRESS
A2A1A0
LLL56 (decimal), 38 (hexadecimal)
LLH57 (decimal), 39 (hexadecimal)
LHL58 (decimal), 3A (hexadecimal)
LHH59 (decimal), 3B (hexadecimal)
HLL60 (decimal), 3C (hexadecimal)
HLH61 (decimal), 3D (hexadecimal)
HHL62 (decimal), 3E (hexadecimal)
HHH63 (decimal), 3F (hexadecimal)

The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read is selected, while a low (0) selects a write operation.