SBAS451B October   2008  – August  2015 PCM1789

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Digital Input/Output
    6. 6.6  Electrical Characteristics: DAC
    7. 6.7  Electrical Characteristics: Power-Supply Requirements
    8. 6.8  System Clock Timing Requirements
    9. 6.9  Audio Interface Timing Requirements
    10. 6.10 Three-Wire Timing Requirements
    11. 6.11 SCL and SDA Timing Requirements
    12. 6.12 Typical Characteristics
      1. 6.12.1 Digital Filter
      2. 6.12.2 Digital De-Emphasis Filter
      3. 6.12.3 Dynamic Performance
      4. 6.12.4 Output Spectrum
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Outputs
      2. 7.3.2  Voltage Reference VCOM
      3. 7.3.3  System Clock Input
      4. 7.3.4  Reset Operation
      5. 7.3.5  ZERO Flag
      6. 7.3.6  AMUTE Control
      7. 7.3.7  Three-Wire (SPI) Serial Control
      8. 7.3.8  Control Data Word Format
      9. 7.3.9  Register Write Operation
      10. 7.3.10 Timing Requirements
      11. 7.3.11 Two-wire (I2C) Serial Control
      12. 7.3.12 Packet Protocol
      13. 7.3.13 Write Operation
      14. 7.3.14 Read Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sampling Mode
      2. 7.4.2 Audio Serial Port Operation
      3. 7.4.3 Audio Data Interface Formats and Timing
      4. 7.4.4 Audio Interface Timing
      5. 7.4.5 Synchronization with the Digital Audio System
      6. 7.4.6 MODE Control
      7. 7.4.7 Parallel Hardware Control
    5. 7.5 Register Maps
      1. 7.5.1 Control Register Definitions (Software Mode Only)
      2. 7.5.2 Register Definitions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Connection Diagrams
      2. 8.1.2 Power Supply and Grounding
      3. 8.1.3 Low-Pass Filter and Differential-to-Single-Ended Converter For DAC Outputs
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Hardware Control Method
        2. 8.2.2.2 Audio Input
        3. 8.2.2.3 Audio Output
        4. 8.2.2.4 Master Clock
    3. 8.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The PCM1789 is a high-performance stereo DAC targeted for consumer audio applications such as Blu-ray Disc players and DVD players, as well as home multi-channel audio applications (such as home theater and A/V receivers). The PCM1789 consists of a two-channel DAC. The DAC output type is fixed with a differential configuration. The PCM1789 supports 16-, 20-, 24-, 32-bit linear PCM input data in I2S and left-justified audio formats, and 24-bit linear PCM input data in right-justified and DSP formats with various sampling frequencies from 8 kHz to 192 kHz. The PCM1789 offers three modes for device control: two-wire I2C software, three-wire SPI software, and hardware.

  • Audio data interface formats: I2S, LJ, RJ, DSP
  • Audio data word length: 16, 20, 24, 32 Bits
  • Audio data format: MSB first, twos complement

7.2 Functional Block Diagram

PCM1789 fbd_bas451.gif

7.3 Feature Description

7.3.1 Analog Outputs

The PCM1789 includes a two-channel DAC, with a pair of differential voltage outputs pins. The full-scale output voltage is (1.6 × VCC1) VPP in differential output mode. A dc-coupled load is allowed in addition to an ac-coupled load, if the load resistance conforms to the specification. These balanced outputs are each capable of driving 0.8 VCC1 (4 VPP) typical into a 5-kΩ ac-coupled or 15-kΩ dc-coupled load with VCC1 = +5 V. The internal output amplifiers for VOUTL and VOUTR are biased to the dc common voltage, equal to 0.5 VCC1.

The output amplifiers include an RC continuous-time filter that helps to reduce the out-of-band noise energy present at the DAC outputs as a result of the noise shaping characteristics of the PCM1789 delta-sigma (ΔΣ) DACs. The frequency response of this filter is shown in the Analog Filter Characteristic (Figure 11) of the Typical Characteristics. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for most applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Application Information section.

7.3.2 Voltage Reference VCOM

The PCM1789 includes a pin for the common-mode voltage output, VCOM. This pin should be connected to the analog ground via a decoupling capacitor. This pin can also be used to bias external high-impedance circuits, if they are required.

7.3.3 System Clock Input

The PCM1789 requires an external system clock input applied at the SCKI input for DAC operation. The system clock operates at an integer multiple of the sampling frequency, or fS. The multiples supported in DAC operation include 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS, and 1152 fS. Details for these system clock multiples are shown in Table 1. The System Clock Timing Requirements table shows the SCKI timing requirements.

Table 1. System Clock Frequencies for Common Audio Sampling Rates

DEFAULT
SAMPLING
MODE
SAMPLING FREQUENCY, fS
(kHz)
SYSTEM CLOCK FREQUENCY (MHz)
128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 1152 fS
Single rate 8 N/A N/A 2.0480 3.0720 4.0960 6.1440 9.2160
16 2.0480 3.0720 4.0960 6.1440 8.1920 12.2880 18.4320
32 4.0960 6.1440 8.1920 12.2880 16.3840 24.5760 36.8640
44.1 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 N/A
48 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 N/A
Dual rate 88.2 11.2896 16.9344 22.5792 33.8688 N/A N/A N/A
96 12.2880 18.4320 24.5760 36.8640 N/A N/A N/A
Quad rate 176.4 22.5792 33.8688 N/A N/A N/A N/A N/A
192 24.5760 36.8640 N/A N/A N/A N/A N/A
PCM1789 ai_tim_scki_bas451.gifFigure 19. System Clock Timing Diagram

7.3.4 Reset Operation

The PCM1789 has both an internal power-on reset circuit and an external reset circuit. The sequences for both reset circuits are shown in Figure 20 and Figure 21. Figure 20 illustrates the timing at the internal power-on reset. Initialization is triggered automatically at the point where VDD exceeds 2.2 V typical, and the internal reset is released after 3846 SCKI clock cycles from power-on, if RST is held high and SCKI is provided. VOUTx from the DAC is forced to the VCOM level initially (that is, 0.5 × VCC1) and settles at a specified level according to the rising VCC. If synchronization among SCKI, BCK, and LRCK is maintained, VOUT provides an output that corresponds to DIN after 3846 SCKI clocks from power-on. If the synchronization is not held, the internal reset is not released, and both operating modes are maintained at reset and power-down states. After synchronization forms again, the DAC returns to normal operation with the previous sequences.

Figure 21 illustrates a timing diagram at the external reset. RST accepts an externally-forced reset with RST low, and provides a device reset and power-down state that achieves the lowest power dissipation state available in the PCM1789. If RST goes from high to low under synchronization among SCKI, BCK, and LRCK, the internal reset is asserted, all registers and memory are reset, and finally, the PCM1789 enters into all power-down states. At the same time, VOUT is immediately forced into the AGND1 level. To begin normal operation again, toggle RST high; the same power-up sequence is performed as the power-on reset shown in Figure 20.

The PCM1789 does not require particular power-on sequences for VCC and VDD; it allows VDD on and then VCC on, or VCC on and then VDD on. From the viewpoint of the Absolute Maximum Ratings, however, simultaneous power-on is recommended for avoiding unexpected responses on VOUTx. Figure 20 illustrates the response for VCC on with VDD on.

PCM1789 ai_tim_por_bas451.gifFigure 20. Power-On-Reset Timing Requirements
PCM1789 ai_tim_ex_reset_bas451.gifFigure 21. External Reset Timing Requirements

7.3.5 ZERO Flag

The PCM1789 has two ZERO flag pins (ZERO1 and ZERO2) that can be assigned to the combinations shown in Table 2. Zero flag combinations are selected through the AZRO bit in control register 22 (16h). If the input data of all the assigned channels remain at '0' for 1024 sampling periods (LRCK clock periods), the ZERO1/2 bits are set to a high level, logic '1' state. Furthermore, if the input data of any of the assigned channels read '1', the ZERO1/2 are set to a low level, logic '0' state, immediately. Zero data detection is supported for 16-/20-/24-bit data width, but is not supported for 32-bit data width.

The active polarity of the zero flag output can be inverted through the ZREV bit in control register 22 (16h). The reset default is active high for zero detection.

In parallel hardware control mode, ZERO1 and ZERO2 are fixed with combination A, shown in Table 2.

Table 2. Zero Flag Outputs Combination

ZERO FLAG COMBINATION ZERO1 ZERO2
A Left channel Right channel
B Left channel or right channel Left channel and right channel

Note that the ZERO2 pin is multiplexed with AMUTEO pin. Selection of ZERO2 or AMUTEO can be changed through the MZSEL bit in control register 22 (16h). The default setting after reset is the selection of ZERO2.

7.3.6 AMUTE Control

The PCM1789 has an AMUTE control input, status output pins, and functionality. AMUTEI is the input control pin of the internal analog mute circuit. An AMUTEI low input causes the DAC output to cut-off from the digital input and forces it to the center level (0.5 VCC1). AMUTEO is the status output pin of the internal analog mute circuit. AMUTEO low indicates the analog mute control circuit is active because of a programmed condition (such as an SCKI halt, asynchronous detect, zero detect, or by the DAC disable command) that forces the DAC outputs to a center level. Because AMUTEI is not terminated internally and AMUTEO is an open-drain output, pull-ups by the appropriate resistors are required for proper operation.

Note that the AMUTEO pin is multiplexed with the ZERO2 pin. The desired pin is selected through the MZSEL bit in control register 22 (16h). The default setting is the selection of the ZERO2 pin.

Additionally, because the AMUTEI pin control and power-down control in register (OPEDA when high, PSMDA when low) do not function together, AMUTEI takes priority over power-down control. Therefore, power-down control is ignored during AMUTEI low, and AMUTEI low forces the DAC output to a center level (0.5 VCC1) even if power-down control is asserted.

7.3.7 Three-Wire (SPI) Serial Control

The PCM1789 includes an SPI-compatible serial port that operates asynchronously with the audio serial interface. The control interface consists of MD/SDA/DEMP, MC/SCL/FMT, and MS/ADR0/RSV. MD is the serial data input used to program the mode control registers. MC is the serial bit clock that shifts the data into the control port. MS is the select input used to enable the mode control port.

7.3.8 Control Data Word Format

All single write operations via the serial control port use 16-bit data words. Figure 22 shows the control data word format. The first bit (fixed at '0') is for write operation. After the first bit are seven other bits, labeled ADR[6:0], that set the register address for the write operation. ADR6 is determined by the status of the MODE pin. ADR5 is determined by the state of the ADR5/ADR1/RSV pin. A maximum of four PCM1789s can be connected on the same bus at any one time. Each PCM1789 responds when receiving its own register address. The eight least significant bits (LSBs), D[7:0] on MD, contain the data to be written to the register address specified by ADR[6:0].

PCM1789 ai_op_ctrl_md_bas451.gifFigure 22. Control Data Word Format for MD

7.3.9 Register Write Operation

Figure 23 shows the functional timing diagram for single write operations on the serial control port. MS is held at a high state until a register is to be written to. To start the register write cycle, MS is set to a low state. 16 clocks are then provided on MC, corresponding to the 16 bits of the control data word on MD. After the 16th clock cycle has been completed, MS is set high to latch the data into the indexed mode control register.

In addition to single write operations, the PCM1789 also supports multiple write operations, which can be performed by sending the N-bytes (where N ≤ 9) of the 8-bit register data that follow after the first 16-bit register address and register data, while keeping the MC clocks and MS at a low state. Ending a multiple write operation can be accomplished by setting MS to a high state.

PCM1789 ai_op_reg_wr_bas451.gif
1. X = don't care.
Figure 23. Register Write Operation

7.3.10 Timing Requirements

Figure 24 shows a detailed timing diagram for the three-wire serial control interface. These timing parameters are critical for proper control port operation.

PCM1789 ai_tim_ctrl_3wire_bas451.gifFigure 24. Three-Wire Serial Control Interface Timing

7.3.11 Two-wire (I2C) Serial Control

The PCM1789 supports an I2C-compatible serial bus and data transmission protocol for fast mode configured as a slave device. This protocol is explained in the I2C specification 2.0.

The PCM1789 has a 7-bit slave address, as shown in Figure 25. The first five bits are the most significant bits (MSBs) of the slave address and are factory-preset to 10011. The next two bits of the address byte are selectable bits that can be set by MS/ADR0/RSV and ADR5/ADR1/RSV. A maximum of four PCM1789s can be connected on the same bus at any one time. Each PCM1789 responds when it receives its own slave address.

PCM1789 ai_slave_addy_bas451.gifFigure 25. Slave Address

7.3.12 Packet Protocol

A master device must control the packet protocol, which consists of a start condition, a slave address with the read/write bit, data if a write operation is required, an acknowledgment if a read operation is required, and a stop condition. The PCM1789 supports both slave receiver and transmitter functions. Details about DATA for both write and read operations are described in Figure 26.

PCM1789 ai_tim_i2c_packet_bas451.gif
1. R/W: Read operation if 1; write operation otherwise.
2. ACK: Acknowledgment of a byte if 0, not Acknowledgment of a byte if 1.
3. DATA: Eight bits (byte); details are described in the Write Operation and Read Operation sections.
Figure 26. I2C Packet Control Protocol

7.3.13 Write Operation

The PCM1789 supports a receiver function. A master device can write to any PCM1789 register using single or multiple accesses. The master sends a PCM1789 slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When valid data are received, the index register automatically increments by one. When the register address reaches &h4F, the next value is &h40. When undefined registers are accessed, the PCM1789 does not send an acknowledgment. Figure 27 illustrates a diagram of the write operation. The register address and write data are in 8-bit, MSB-first format.

PCM1789 ai_op_wr_frame_bas451.gif
NOTE: M = Master device, S = Slave device, St = Start condition, W = Write, ACK = Acknowledge, and Sp = Stop condition.
Figure 27. Framework for Write Operation

7.3.14 Read Operation

A master device can read the registers of the PCM1789. The value of the register address is stored in an indirect index register in advance. The master sends the PCM1789 slave address with a read bit after storing the register address. Then the PCM1789 transfers the data that the index register points to. Figure 28 shows a diagram of the read operation.

PCM1789 ai_op_rd_frame_bas451.gif
1. The slave address after the repeated start condition must be the same as the previous slave address.
NOTE: M = Master device, S = Slave device, St = Start condition, Sr = Repeated start condition, W = Write, R = Read, ACK = Acknowledge, NACK = Not acknowledge, and Sp = Stop condition.
Figure 28. Framework for Read Operation

7.4 Device Functional Modes

7.4.1 Sampling Mode

The PCM1789 supports three sampling modes (single rate, dual rate, and quad rate) in DAC operation. In single rate mode, the DAC operates at an oversampling frequency of x128 (except when SCKI = 128 fS and 192 fS); this mode is supported for sampling frequencies less than 50 kHz. In dual rate mode, the DAC operates at an oversampling frequency of x64; this mode is supported for sampling frequencies less than 100 kHz. In quad rate mode, the DAC operates at an oversampling frequency of x32. The sampling mode is automatically selected according to the ratio of system clock frequency and sampling frequency by default (that is, single rate for 512 fS, 768 fS, and 1152 fS; dual rate for 256 fS and 384 fS; and quad rate for 128 fS and 192 fS), but manual selection is also possible for specified combinations through the serial mode control register.

Table 3 and Figure 29 show the relationship among the oversampling rate (OSR) of the digital filter and ΔΣ modulator, the noise-free shaped bandwidth, and each sampling mode setting.

Table 3. Digital Filter OSR, Modulator OSR, and Noise-Free Shaped Bandwidth for Each Sampling Mode

SAMPLING MODE REGISTER SETTING SYSTEM CLOCK FREQUENCY
(xfS)
NOISE-FREE SHAPED BANDWIDTH(1)
(kHz)
DIGITAL FILTER OSR MODULATOR OSR
fS = 48 kHz fS = 96 kHz fS = 192 kHz
Auto 512, 768, 1152 40 N/A N/A ×8 x128
256, 384 20 40 N/A x8 x64
128, 192(2) 10 20 40 x4 x32
Single 512, 768, 1152 40 N/A N/A x8 x128
256, 384 40 N/A N/A x8 x128
128, 192(2) 20 N/A N/A x4 x64
Dual 256, 384 20 40 N/A x8 x64
128, 192(2) 20 40 N/A x4 x64
Quad 128, 192(2) 10 20 40 x4 x32
(1) Bandwidth in which noise is shaped out.
(2) Quad mode filter characteristic is applied.
PCM1789 ai_mod_filt_char_bas451.gifFigure 29. ΔΣ Modulator and Digital Filter Characteristic

7.4.2 Audio Serial Port Operation

The PCM1789 audio serial port consists of three signals: BCK, LRCK, and DIN. BCK is a bit clock input. LRCK is a left/right word clock or frame synchronization clock input. DIN is the audio data input for VOUTL/R.

7.4.3 Audio Data Interface Formats and Timing

The PCM1789 supports six audio data interface formats: 16-/20-/24-/32-bit I2S, 16-/20-/24-/32-bit left-justified, 24-bit right-justified, 16-bit right-justified, 24-bit left-justified mode DSP, and 24-bit I2S mode DSP. In the case of I2S, left-justified, and right-justified data formats, 64 BCKs, 48 BCKs, and 32 BCKs per LRCK period are supported; however, 48 BCKs are limited to 192/384/768 fS SCKI, and 32 BCKs are limited to 16-bit right-justified only. The audio data formats are selected by MC/SCL/FMT in hardware control mode and by the FMTDA[2:0] bits in control register 17 (11h) in software control mode. All data must be in binary twos complement and MSB first.

Table 4 summarizes the applicable formats and describes the relationships among them and the respective restrictions with mode control. Figure 30 through Figure 34 show six audio interface data formats.

Table 4. Audio Data Interface Formats and Sampling Rate, Bit Clock, and System Clock Restrictions

CONTROL MODE FORMAT DATA BITS MAX LRCK FREQUENCY (fS) SCKI RATE (xfS) BCK RATE (xfS)
Software control I2S/Left-Justified 16/20/24/32(1) 192 kHz 128 to 1152(2) 64, 48
Right-Justified 24, 16 192 kHz 128 to 1152(2) 64, 48, 32 (16 bit)(3)
I2S/Left-Justified DSP 24 192 kHz 128 to 768 64
Hardware control I2S/Left-Justified 16/20/24/32(1) 192 kHz 128 to 1152(2) 64, 48
(1) 32-bit data length is acceptable only for BCK = 64 fS and when using I2S or Left-Justified format.
(2) 1152 fS is acceptable only for fS = 32 kHz, BCK = 64 fS, and when using I2S, Left-Justified, or 24-bit Right-Justified format.
(3) BCK = 32 fS is supported only for 16-bit data length.
PCM1789 ai_tim_audio_16-32_i2s_bas451.gifFigure 30. Audio Data Format: 16-/20-/24-/32-Bit I2S
(N = 15/19/23/31, M = 14/18/22/30, and L = 13/17/21/29)
PCM1789 ai_tim_audio_16-32_lj_bas451.gifFigure 31. Audio Data Format: 16-/20-/24-/32-Bit Left-Justified
(N = 15/19/23/31, M = 14/18/22/30, and L = 13/17/21/29)
PCM1789 ai_tim_audio_24_rj_bas451.gifFigure 32. Audio Data Format: 24-Bit Right-Justified
PCM1789 ai_tim_audio_16_rj_bas451.gifFigure 33. Audio Data Format: 16-Bit Right-Justified
PCM1789 ai_tim_audio_24_dsp_bas451.gifFigure 34. Audio Data Format: 24-Bit DSP Format

7.4.4 Audio Interface Timing

Figure 35 and Audio Interface Timing Requirements describe the detailed audio interface timing specifications.

PCM1789 ai_tim_audio_iface_lj-i2s_bas451.gifFigure 35. Audio Interface Timing Diagram for Left-Justified, Right-Justified, I2S, and DSP Data Formats

7.4.5 Synchronization with the Digital Audio System

The PCM1789 operates under the system clock (SCKI) and the audio sampling rate (LRCK). Therefore, SCKI and LRCK must have a specific relationship. The PCM1789 does not need a specific phase relationship between the audio interface clocks (LRCK, BCK) and the system clock (SCKI), but does require a specific frequency relationship (ratiometric) between LRCK, BCK, and SCKI.

If the relationship between SCKI and LRCK changes more than ±2 BCK clocks because of jitter, sampling frequency change, etc., the DAC internal operation stops within 1/fS, and the analog output is forced into VCOM (0.5 VCC1) until re-synchronization among SCKI, LRCK, and BCK completes, and then either 38/fS (single, dual rate) or 29/fS (quad rate) passes. In the event the change is less than ±2 BCKs, re-synchronization does not occur, and this analog output control and discontinuity does not occur.

Figure 36 shows the DAC analog output during loss of synchronization. During undefined data periods, some noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined (or zero) data to normal data creates a discontinuity of data on the analog outputs, which may then generate some noise in the audio signal.

The DAC outputs (VOUTx) hold the previous state if the system clock halts, but the asynchronous and re-synchronization processes will occur after the system clock resumes.

PCM1789 ai_tim_dac_sync_loss_bas451.gifFigure 36. DAC Outputs During Loss of Synchronization

7.4.6 MODE Control

The PCM1789 includes three mode control interfaces with three oversampling configurations, depending on the input state of the MODE pin, as shown in Table 5. The pull-up and pull-down resistors must be 220 kΩ ±5%.

Table 5. Interface Mode Control Selection

MODE MODE CONTROL INTERFACE
Tied to DGND Two-wire (I2C) serial control, selectable oversampling configuration
Pull-down resistor to DGND Two-wire parallel control, auto mode oversampling configuration
Pull-up resistor to VDD Three-wire (SPI) serial control, selectable oversampling configuration, ADR6 = '0'
Tied to VDD Three-wire (SPI) serial control, selectable oversampling configuration, ADR6 = '1'

The input state of the MODE pin is sampled at the moment of power-on, or during a low-to-high transition of the RST pin, with the system clock input. Therefore, input changes after reset are ignored until the next power-on or reset. From the mode control selection described in Table 5, the functions of four pins are changed, as shown in Table 6.

Table 6. Pin Functions for Interface Mode

PIN PIN ASSIGNMENTS
SPI I2C H/W
21 MD (input) SDA (input/output) DEMP (input)
22 MC (input) SCL (input) FMT (input)
23 MS (input) ADR0 (input) RSV (input, low)
24 ADR5 (input) ADR1 (input) RSV (input, low)

In serial mode control, the actual mode control is performed by register writes (and reads) through the SPI- or I2C-compatible serial control port. In parallel mode control, two specific functions are controlled directly through the high/low control of two specific pins, as described in the following section.

7.4.7 Parallel Hardware Control

The functions shown in Table 7 and Table 8 are controlled by two pins, DEMP and FMT, in parallel hardware control mode. The DEMP pin controls the 44.1-kHz digital de-emphasis function of both channels. The FMT pin controls the audio interface format for both channels.

Table 7. DEMP Functionality

DEMP DESCRIPTION
Low De-emphasis off
High 44.1 kHz de-emphasis on

Table 8. FMT Functionality

FMT DESCRIPTION
Low 16-/20-/24-/32-bit I2S format
High 16-/20-/24-/32-bit left-justified format

7.5 Register Maps

7.5.1 Control Register Definitions (Software Mode Only)

The PCM1789 has many user-programmable functions that are accessed via control registers, and are programmed through the SPI or I2C serial control port. Table 9 shows the available mode control functions along with reset default conditions and associated register addresses. Table 10 lists the register map.

Table 9. User-Programmable Mode Control Functions

FUNCTION RESET DEFAULT REGISTER(1) LABEL
Mode control register reset Normal operation 16 MRST
System reset Normal operation 16 SRST
Analog mute function control Mute disabled 16 AMUTE[3:0]
Sampling mode selection Auto 16 SRDA[1:0]
Power-save mode selection Power save 17 PSMDA
Audio interface format selection I2S 17 FMTDA[2:0]
Operation control Normal operation 18 OPEDA
Digital filter roll-off control Sharp roll-off 18 FLT
Output phase selection Normal 19 REVDA[2:1]
Soft mute control Mute disabled 20 MUTDA[2:1]
Zero flag Not detected 21 ZERO[2:1]
Digital attenuation mode 0 dB to –63 dB, 0.5-dB step 22 DAMS
Digital de-emphasis function control Disabled 22 DEMP[1:0]
AMUTEO/ZERO flag selection ZERO2 22 MZSEL
Zero flag function selection ZERO1: left-channel
ZERO2: right-channel
22 AZRO
Zero flag polarity selection High for detection 22 ZREV
Digital attenuation level setting 0 dB, no attenuation 24, 25 ATDAx[7:0]
(1) If ADR6 or ADR5 is high, the register address must be changed to the number shown + offset; offset is 32, 64 and 96 according to state of ADR6, 5 (01, 10 and 11).

Table 10. Register Map

ADR[6:0](1) DATA[7:0]
DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
16 10 MRST SRST AMUTE3 AMUTE2 AMUTE1 AMUTE0 SRDA1 SRDA0
17 11 PSMDA RSV(2) RSV(2) RSV(2) RSV(2) FMTDA2 FMTDA1 FMTDA0
18 12 RSV(2) RSV(2) RSV(2) OPEDA RSV(2) RSV(2) RSV(2) FLT
19 13 RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) REVDA2 REVDA1
20 14 RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) MUTDA2 MUTDA1
21 15 RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) ZERO2 ZERO1
22 16 DAMS RSV(2) DEMP1 DEMP0 MZSEL RSV(2) AZRO ZREV
23 17 RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2)
24 18 ATDA17 ATDA16 ATDA15 ATDA14 ATDA13 ATDA12 ATDA11 ATDA10
25 19 ATDA27 ATDA26 ATDA25 ATDA24 ATDA23 ATDA22 ATDA21 ATDA20
(1) If ADR6 or ADR5 is high, the register address must be changed to the number shown + offset; offset is 32, 64 and 96 according to state of ADR6, 5 (01, 10 and 11).
(2) RSV must be set to '0'.

7.5.2 Register Definitions

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
16 10 MRST SRST AMUTE3 AMUTE2 AMUTE1 AMUTE0 SRDA1 SRDA0
MRST Mode control register reset
This bit sets the mode control register reset to the default value. Pop noise may be generated. Returning the MRST bit to '1' is unnecessary because it is automatically set to '1' after the mode control register is reset.
Default value = 1.
MRST Mode control register reset
0 Set default value
1 Normal operation (default)
SRST System reset
This bit controls the system reset, which includes the resynchronization between the system clock and sampling clock, and DAC operation restart. The mode control register is not reset and the PCM1789 does not go into a power-down state. Returning the SRST bit to '1' is unnecessary; it is automatically set to '1' after triggering a system reset.
Default value = 1.
SRST System reset
0 Resynchronization
1 Normal operation (default)
AMUTE[3:0] Analog mute function control
These bits control the enabling/disabling of each source event that triggers the analog mute control circuit.
Default value = 0000.
AMUTE Analog mute function control
xxx0 Disable analog mute control by SCKI halt
xxx1 Enable analog mute control by SCKI halt
xx0x Disable analog mute control by asynchronous detect
xx1x Enable analog mute control by asynchronous detect
x0xx Disable analog mute control by ZERO1 and ZERO2 detect
x1xx Enable analog mute control by ZERO1 and ZERO2 detect
0xxx Disable analog mute control by DAC disable command
1xxx Enable analog mute control by DAC disable command
SRDA[1:0] Sampling mode selection
These bits control the sampling mode of DAC operation. In Auto mode, the sampling mode is automatically set according to multiples between the system clock and sampling clock: single rate for 512 fS, 768 fS, and 1152 fS, dual rate for 256 fS or 384 fS, and quad rate for 128 fS and 192 fS.
Default value = 00.
SRDA Sampling mode selection
00 Auto (default)
01 Single rate
10 Dual rate
11 Quad rate

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
17 11 PSMDA RSV RSV RSV RSV FMTDA2 FMTDA1 FMTDA0
PSMDA Power-save mode selection
This bit selects the power-save mode for the OPEDA function. When PSMDA = 0, OPEDA controls the power-save mode and normal operation. When PSMDA = 1, OPEDA functions controls the DAC disable (not power-save mode) and normal operation.
Default value: 0.
PSMDA Power-save mode selection
0 Power-save enable mode (default)
1 Power-save disable mode
RSV Reserved
Reserved; do not use.
FMTDA[2:0] Audio interface format selection
These bits control the audio interface format for DAC operation. Details of the format and any related restrictions with the system clock are described in the Audio Data Interface Formats and Timing section.
Default value: 0000 (16-/20-/24-/32-bit I2S format).
FMTDA Audio interface format selection
000 16-/20-/24-/32-bit I2S format (default)
001 16-/20-/24-/32-bit left-justified format
010 24-bit right-justified format
011 16-bit right-justified format
100 24-bit I2S mode DSP format
101 24-bit left-justified mode DSP format
110 Reserved
111 Reserved
DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
18 12 RSV RSV RSV OPEDA RSV RSV RSV FLT
RSV Reserved
Reserved; do not use.
OPEDA Operation control
This bit controls the DAC operation mode. In operation disable mode, the DAC output is cut off from DIN and the internal DAC data are reset. If PSMDA = 1, the DAC output is forced into VCOM. If PSMDA = 0, the DAC output is forced into AGND and the DAC goes into a power-down state. For normal operating mode, this bit must be '0'. The serial mode control is effective during operation disable mode.
Default value: 0.
OPEDA Operation control
0 Normal operation
1 Operation disable with or without power save
FLT Digital filter roll-off control
This bit allows users to select the digital filter roll-off that is best suited to their applications. Sharp and slow filter roll-off selections are available. The filter responses for these selections are shown in the Typical Characteristics sections of this data sheet.
Default value: 0.
FLT Digital filter roll-off control
0 Sharp roll-off
1 Slow roll-off

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
19 13 RSV RSV RSV RSV RSV RSV REVDA2 REVDA1
RSV Reserved
Reserved; do not use.
REVDA[2:1] Output phase selection
These bits are used to control the phase of the DAC analog signal outputs.
Default value: 00.
REVDA Output phase selection
x0 Left channel normal output
x1 Left channel inverted output
0x Right channel normal output
1x Right channel inverted output
DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
20 14 RSV RSV RSV RSV RSV RSV MUTDA2 MUTDA1
RSV Reserved
Reserved; do not use.
MUTDA[2:1] Soft Mute control
These bits are used to enable or disable the Soft Mute function for the corresponding DAC outputs, VOUTx. The Soft Mute function is incorporated into the digital attenuators. When mute is disabled (MUTDA[2:1] = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTDA[2:1] = 1, the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation. By setting MUTDA[2:1] = 0, the attenuator is increased to the last attenuation level in the same manner as it is for decreasing levels. This configuration reduces pop and zipper noise during muting of the DAC output. This Soft Mute control uses the same resource of digital attenuation level setting. Mute control has priority over the digital attenuation level setting.
Default value: 00.
MUTDA Soft Mute control
x0 Left channel mute disabled
x1 Left channel mute enabled
0x Right channel mute disabled
1x Right channel mute enabled
DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
21 15 RSV RSV RSV RSV RSV RSV ZERO2 ZERO1
RSV Reserved
Reserved; do not use.
ZERO[2:1] Zero flag (read-only)
These bits indicate the present status of the zero detect circuit for each DAC channel; these bits are read-only.
ZERO Zero flag
x0 Left channel zero input not detected
x1 Left channel zero input detected
0x Right channel zero input not detected
1x Right channel zero input detected

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
22 16 DAMS RSV DEMP1 DEMP0 MZSEL RSV AZRO ZREV
DAMS Digital attenuation mode
This bit selects the attenuation mode.
Default value: 0.
DAMS Digital attenuation mode
0 Fine step: 0.5-dB step for 0 dB to –63 dB range (default)
1 Wide range: 1-dB step for 0 dB to –100 dB range
RSV Reserved
Reserved; do not use.
DEMP[1:0] Digital de-emphasis function/sampling rate control
These bits are used to disable and enable the various sampling frequencies of the digital de-emphasis function.
Default value: 00.
DEMP Digital de-emphasis function/sampling rate control
00 Disable (default)
01 48 kHz enable
10 44.1 kHz enable
11 32 kHz enable
MZSEL AMUTEO/ZERO flag selection
This bit is used to select the function of the ZERO2 pin.
Default value: 0.
MZSEL AMUTEO/ZERO flag selection
0 The ZERO2 pin functions as ZERO2 (default).
1 The ZERO2 pin functions as AMUTEO.
AZRO Zero flag channel combination selection
This bit is used to select the zero flag channel combination for ZERO1 and ZERO2.
Default value: 0.
AZRO Zero flag combination selection
0 Combination A: ZERO1 = left channel, ZERO2 = right channel (default)
1 Combination B: ZERO1 = left channel or right channel, ZERO2 = left channel and right channel
ZREV Zero flag polarity selection
This bit controls the polarity of the zero flag pin.
Default value: 0.
ZREV Zero flag polarity selection
0 High for zero detect (default)
1 Low for zero detect
DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
23 17 RSV RSV RSV RSV RSV RSV RSV RSV
24 18 ATDA17 ATDA16 ATDA15 ATDA14 ATDA13 ATDA12 ATDA11 ATDA10
25 19 ATDA27 ATDA26 ATDA25 ATDA24 ATDA23 ATDA22 ATDA21 ATDA20
RSV Reserved
Reserved; do not use.
ATDAx[7:0] Digital attenuation level setting
Where x = 1 to 2, corresponding to the DAC output (VOUTx).
Both DAC outputs (VOUTL and VOUTR) have a digital attenuation function. The attenuation level can be set from 0 dB to R dB, in S-dB steps. Changes in attenuator levels are made by incrementing or decrementing one step (S dB) for every 8/fS time interval until the programmed attenuator setting is reached. Alternatively, the attenuation level can be set to infinite attenuation (or mute). R (range) and S (step) is –63 and 0.5 for DAMS = 0, and –100 and 1.0 for DAMS = 1, respectively. The DAMS bit is defined in register 22 (16h). Table 11 shows attenuation levels for various settings.
The attenuation level for each channel can be set individually using the following formula:
Attenuation level (dB) = S × (ATDAx[7:0]DEC – 255)
where ATDAx[7:0]DEC = 0 through 255.
For ATDAx[7:0]DEC = 0 through 128 with DAMS = 0, or 0 through 154 with DAMS = 1, attenuation is set to infinite attenuation (mute).
Default value: 1111 1111.

Table 11. Attenuation Levels for Various Settings

ATDAx[7:0] ATTENUATION LEVEL SETTING
BINARY DECIMAL DAMS = 0 DAMS = 1
1111 1111 255 0 dB, no attenuation (default) 0 dB, no attenuation (default)
1111 1110 254 –0.5 dB –1 dB
1111 1101 253 –1.0 dB –2 dB
... ... ... ...
1001 1100 156 –45.9 dB –99 dB
1001 1011 155 –50.0 dB –100 dB
1001 1010 154 –50.5 dB Mute
... ... ... ...
1000 0010 130 –62.5 dB Mute
1000 0001 129 –63.0 dB Mute
0000 0000 128 Mute Mute
... ... ... ...
0000 0000 0 Mute Mute