9.3.2.1 Mic Bias

The PCM186x-Q1 can provide a microphone bias to power and bias microphones at 2.6 V on pin 5. Decouple or filter the Mic Bias pin with an external capacitor. Mic Bias is typically used with a electret microphone. The internal regulator, as well as an on-chip terminating resistor to GND can also be enabled using register MIC_BIAS_CTRL (Page.3, 0x15). By default, the device is configured to bypass the on-chip resistor. The mic bias pin can be left unconnected if not used.

Table 1. Channel and Gain Selection for Hardware-Controlled Devices

Table 2. MUX, MIX, and Polarity Input Selection⁽¹⁾

9.3.6.1 Attenuation Level

This feature is not designed to be a complete analog gain control. This feature was defined to avoid clipping, and to inform the system microcontroller of a clipping event, to allow the microcontroller (or the end user) to decide if the gain should be increased again.

The attenuation is programmable to –3 dB, –4 dB, –5 dB, or –6 dB.

9.3.6.2 Channel Linking

Depending on the application, users may not want to link input channels, however, for the majority of stereo input applications, its strongly recommended to set the system to track gain across inputs, to maintain balance.

The auto PGA clipping suppression control has the settings shown in Table 3.

Table 3. Auto Clipping Suppression Control Registers

9.3.8.1 Stereo PCM Sources

The PCM186x-Q1 can support stereo PCM data on GPIO pins so that I²S sources, such as wireless modules can have their data mixed with the incoming analog content. The clock rate of the incoming data (known as DIN) must be synchronous with the PCM186x-Q1 software-controlled device main clocks. There is no integrated sample rate converter on-chip. The DIN signal can be received on GPIO0, 1, 2, or 3, and configured on GPIO_FUNC_X (Page.0 0x10 and 0x11). The incoming data are then driven to the digital mixer running on DSP2.

The audio format can be configured separately from the output serial port using register RX_TDM_OFFSET (P0, 0x0E).

Inputs can be mixed and volume-controlled before routing to a digital amplifier. Typical uses could be the connection to a Bluetooth™ module. The mixing and crossfading is done all in the PCM186x-Q1, rather than a hard switch in external logic. The on-chip PLL also helps create the system master clock (SCKOUT) for poorly designed I²S Bluetooth modules that do not provide a system clock to drive the system DACs.

If the stereo PCM data source has a requirement to drive the audio clock pins when transmitting in a system where the PCM186x-Q1 has not been set to slave yet, the PCM186x-Q1 does not suffer any damage during clock driver contention. However, the PCM186x-Q1 will have some irregular output due to clock errors. In systems with additional stereo PCM sources that need to be master (such as a S/PDIF receive), set the PCM186x-Q1 to always be a clock slave, or switch the device from master to slave mode, before enabling the stereo PCM source.

9.3.8.2 Digital PDM Microphones

Up to four digital microphones are supported on the PCM1864-Q1 and PCM1865-Q1, using a shared output clock (configured from GPIO2) and two data lines, GPIO0 or GPIO1. Two digital microphones are supported on the PCM1862-Q1 and PCM1863-Q1, mainly using GPIO1 as the data input. The PCM1860-Q1 or PCM1861-Q1 does not support digital microphones. The typical connection and protocol diagrams for these microphones are shown in Figure 31 and Figure 32.

Figure 31. Digital Microphone Example Connection

Figure 32. Digital Microphone Protocol

Supported Digital Microphone clock frequency is as follows, and the frequency depends on required operating sampling frequency as follows:

• 2.0480 MHz (32 kHz × 64)
• 2.8224 MHz (44.1 kHz × 64)
• 3.072 MHz (48 kHz × 64)
• 3.072 MHz (96 kHz × 32 )

• Sampling frequency is 32 kHz or 44.1 kHz
• SCK is 256 × f_S.
• Enable Auto Clock Detector (Default)

9.3.9.1 Description

The PCM186x-Q1 family has an extremely flexible clocking architecture. All converters require a master clock (typically, a 2ⁿ power of the sampling rate known as MCK), a bit clock (BCK) that is used to clock the data bit-by-bit out of the device (typically running at 64-f_S to allow up to 32 bits per channel output), and finally a wordclock (left-right clock, LRCK) that is used to set the exact sampling point for the ADC.

The PCM186x-Q1 family can be a clock master (where BCK and LRCK can be internally divided from a provided master clock) or can be a clock slave, where all clocks (MCK, BCK and LRCK) must be provided by an external source.

Unlike many competing devices, the PCM186x-Q1 family can source its master clock from two different sources, either an external crystal, or a CMOS level (3.3 V or 1.8 V) clock, eliminating the usual external crystal oscillator circuit required to source a CMOS clock signal.

The PCM186x-Q1 also differentiates itself by integrating an on-chip phase locked loop (PLL) that can generate real audio-rate clocks from any clock source between 1 MHz and 50 MHz. The PCM1860-Q1 or PCM1861-Q1 hardware-controlled devices have the ability to detect an absence of MCK in slave mode and automatically generate a MCK signal. Software-controlled devices, such as the PCM1862-Q1, PCM1863-Q1, PCM1864-Q1 and PCM1865-Q1 can have their PLL programmed to generate audio clocks based on any incoming clock rate. For example, a 12 MHz clock in the system can be used to generate clocks for a 44.1-kHz system.

9.3.9.2 External Clock-Source Limits

The three different clock sources for the device each have some limits in terms of their input circuitry, as shown in Table 4. These limits are separate from the internal PLL capability.

On PCM1860-Q1 and PCM1861-Q1, the highest standard frequency supported by an XTAL is 96 kHz, because the lowest divider ratio of master clock to LRCK is 256 (24.576 MHz / 256 = 96 kHz). This limitation is not present in the software-controlled devices because the divider ratio is programmable. However, 192 kHz can be supported by using an external CMOS source.

9.3.9.3 Device Clock Distribution and Generation

PLLs can be used in all modes to generate the clocks required to run both fixed-function DSPs. The dividers are automatically configured based on the clock rate detection. The clock architecture shown in Figure 33 allows non-audio clock sources to be used as clock sources and the PCM186x-Q1 to continue to run in a master mode, providing all PCM and I²S clocks for other converters in the system.

Figure 33. PCM186x-Q1 Main Audio Clock Tree and Clock Generation

Target Clock Rates for the ADC, DSP1 and DSP2 can be seen in Table 9 and Table 10. In manual clock configuration modes, the dividers should be set to achieve these targets. In short, for 2-channel devices, DSP1 and DSP2 should be 256x the sampling rate; for 4-channel devices, DSP1 should be configured for 512x the sampling rate, and DSP2 should be 256x.

9.3.9.4 Clocking Modes

As shown in Table 5, there are four different clocking modes available on the device that take advantage of the onboard PLL and clock detection. Advanced clock detection and a smart internal state engine in the PCM186x-Q1 can automatically configure the various dividers in the device (see the Device Clock Distribution and Generation section) with optimized values. Automatic clock configuration is enabled by default, using the register CLKDET_EN (Page.0, 0x20).

9.3.9.4.2 Clock Sources for Software-Controlled Devices

The PCM1862-Q1, PCM1863-Q1, PCM1864-Q1, and PCM1865-Q1 software-controlled devices support a wide range of options for generating the clocks required to operate the ADC section, as well as an interface and other control blocks, as shown in Figure 34.

The clocks for the PLL require a source reference clock. This clock source can be configured on software devices as the XTAL, SCK or BCK.

These software-controlled devices share a similar clock tree for the generation and distribution of clocks, as shown in Figure 33.

Register CLK_MODE (Page.0 0x20) is used to configure the clock configuration. Bits [5:7] configure the OR and MUX for the incoming MCLK.

Register MST_MODE (Page.0 0x20) is used to set the device in master or slave mode. Bits [1:3] set clock sources for the ADC, DSP1 and DSP2. These can mostly be ignored for the most common applications, but are provided for advanced users.

Register MST_SCK_SRC (Page.0 0x20) is used to set the source of the SCKO in master mode. The master mode BCK and LRCK will be a division of this. The selection is either SCKI/XTI or PLL. PLL can be used when you have a non-audio rate reference clock (BCK or SCKI), as well as when you have an SCKI that is much too slow for what is required for SCKO.

Most applications will use XTI/SCKI as the source for master mode SCK.

The CLKDET_EN (Page.0, 0x20) register bit (auto clock detector) is important; the clock detector is mainly functional for slave modes, and for master modes where the master clock is a 256×, 384×, or 512× multiple of the incoming data rate.

The relation between the master mode configuration registers is shown in Table 7.

NOTE

Non audio related master clock sources can be used with the PCM186x-Q1 software -controlled devices providing the PLL is programmed manually. CLKDET_EN should be set to 0.

The result of configurations can be checked by reading registers FS_INFO / CURRENT_BCK_RATIO (Page.0 0x73 and 0x74).

NOTE

In master mode on software-controlled devices, only the following BCK to LRCK ratios are supported: 32x, 48x, 64x and 256x. 128x is not supported

Table 7. Master Mode Clock Configuration Registers

CLOCK MULTIPLEXER	FUNCTION	BITS
MST_SCK_SRC	Master mode SCK source	Page 0, register 0x20, bits[5]
DIVIDER	FUNCTION	BITS
CLK_DIV_PLL_SCK	Clock divider of PLL to SCKOUT divider (for example, master mode or BCK PLL slave mode with SCK for the rest of the system)	Pg0, reg 0x25, bits[0:6]
CLK_DIV_SCK_BCK	Ratio of master clock (SCK) to bit clock (BCK)	Pg0, reg 0x26, bits[0:6]
CLK_DIV_BCK_LRCK	Ratio of bit clock (BCK) to left-right clock (LRCK)	Pg0, reg 0x27, bits[0:6]

Figure 34. PLL Clock Source and Clock Distribution

9.3.9.5 Software-Controlled Devices Manual PLL Calculation

The PCM186x-Q1 has an on-chip PLL with fractional multiplication to generate the clock frequency required by the audio ADC, modulator and digital signal processing blocks. The programmability of the PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input supports clocks varying from 1 MHz to 50 MHz, and is register programmable to enable generation of required sampling rates with fine precision.

The PLL by default is enabled because the on-chip fixed function DSPs require high clock rates to complete all various decimation, mixing, and level-detection functions. The PLL output clock PLLCK is given by Equation 1:

Equation 1.

where

• R = 1, 2, 3, 4, ….. 15, 16
• J = 1, 2, 3, 4,...63, and D = 0000, 0001, 0002...9999
• K = J.D
• P = 1, 2, 3...15

R, J, D, and P are register programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

Examples:

If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000 (that is, an integer multiple), the following conditions must be satisfied:

1 MHz ≤ (PLLCKIN / P) ≤ 20 MHz
64 MHz < (PLLCKIN × K × R / P) < 100 MHz
1 ≤ J ≤ 63

When the PLL is enabled and D ≠ 0000 (that is, a noninteger multiple), the following conditions must be satisfied:

6.667 MHz ≤ (PLLCLKIN / P) ≤ 20 MHz
64 MHz < (PLLCKIN x K x R / P) < 100 MHz
4 ≤ J ≤ 11
R = 1

When the PLL is enabled,

f_Sref = (PLLCLKIN × K × R) / (N × P) :
N is selected so that f_Sref × N = PLLCLKIN × K × R / P is in the allowable range.

Example:

MCLK = 12 MHz and f_Sref = 44.1 kHz, (N=2048)
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example:

MCLK = 12 MHz and f_Sref = 48.0 kHz, (N=2048)
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

The PLL can be programmed using page 0, registers 0x28 thru 0x2D. Turn on the PLL using page 0, register 0x28, D(0). The variable P can be programmed using page 0, register 0x29, D(3:0). The variable R can be programmed using page 0, register 0x2A, D(3:0). The variable J can be programmed using page 0, register 0x2B, D(5:0). The variable D is 14-bits and is programmed into two registers. The MSB portion is programmed using page 0, register 0x2D, D(5:0), and the LSB portion is programmed using page 0, register 0x2C, D(7:0). The variable D is set when the LSB portion is programmed.

Values are programmed in the registers in Table 14.

9.3.9.6 Clock Halt and Error

The status of the halt and error detector can be read from register CLK_ERR_STAT (Page.0, 0x75).

9.3.9.7 Clock Halt and Error Detect

The PCM186x-Q1 has a clock error detection block inside that continues to monitor the ratio of BCK to LRCK.

If a clock error is detected (such as an unexpected number of BCKs per LRCK), then the device goes into standby mode.

If all the clocks are stopped going into the device, then the device shifts into sleep state, and begins Energysense signal detect mode.

When a clock error occurs, the PCM186x-Q1 starts the following sequence:

1. Mute audio output immediately (without volume ramp down)
2. Wait until proper clock is supplied (known as Clock Waiting State)
3. Restart clock detection. The PLL and all clock dividers are reconfigured with the result of the detection.
4. Start fade-in

If the device stops transmitting data, the first step is to read CLK_ERR_STAT (Page.0 0x72). The least significant nibble shows the device status. Value 0x01 suggests Clock Waiting State, at which point the clock error status can be read in register STATE (Page.0 0x75). The clock detection logic is shown in Table 15.

In addition, the device uses an on-chip oscillator to detect errors in the rate of present clocks. That logic is shown in Table 16.

In an application with a non-audio standard SCK coming into the product, the clock error detection on the SCK pin can be ignored by disabling the auto clock detector (CLKDET_EN Page.0 0x20).

9.3.9.8 Changes in Clock Sources and Sample Rates

In slave mode, when changing clock sources, the PCM186x-Q1 requires at least three BCK clocks of no clock or data for the device to reconfigure after clocks resume (if the device is in auto clock config mode).

For example, auto clock config mode: StateA = 48 kHz, change to StateB = 44.1 kHz

For changing from state A to State B:

• Leaving State A
• Hold clocks (or HiZ from external) for 3 BCK minimum
• Change clocks
• Allow ~100 µs (at least 3 BLKs at 48 kHz) for the device to reconfigure
• Data ramp back in on zero-crossing ramp (if zero crossing has not been disabled in software mode)
• Transition to State B complete

In master mode, simply switching the I/O pins on the hardware-controlled devices, or changing the sampling rate register should change the sampling rate.

9.3.10.1 Main Audio ADCs

The SNR of the primary ADCs in the PCM186x-Q1 are 103 dB (for PCM1860-Q1, PCM1862-Q1, PCM1864-Q1), or 110 dB (for PCM1861-Q1, PCM1863-Q1, PCM1865-Q1), with 40-kHz bandwidth that is tightly coupled to dedicated PGAs and input multiplexers. Often in this document, references are made to ADC1L and ADC1R (or CH1_L and CH1_R), the main left and right ADCs present in the PCM1862-Q1, PCM1863-Q1, PCM1864-Q1 and PCM1865-Q1. References to ADC2L and ADC2R are the other pair of left and right ADCs present only in the PCM1864-Q1 and PCM1865-Q1.

9.3.10.2 Secondary ADC: Energysense and Analog Control

The PCM186x-Q1 has a secondary ADC, shown in Figure 35, that is used for signal level detection or dc level change detection.

1. Reset ports not shown.

Figure 35. Secondary ADC Architecture

The secondary ADC has two main purposes in the PCM186x-Q1 family. The primary purpose is to act as a low power signal detection system, to aid with system wakeup from sleep. TI calls this functionality energysense. Other functionality includes the ability to use any spare analog inputs as generic ADC inputs, for connection to simple analog sources, such as voltages from control potentiometers. TI calls this functionality controlsense or dc control.

The secondary ADC is a one-bit, delta-sigma type ADC. The sampling rate is directly connected to the main ADC audio sampling clocks during ACTIVE functionality. When the device is in sleep state, then the secondary ADC switches the clock source to an on-chip oscillator (if there are no other clock sources).

In sleep mode, the inputs are all treated as single-ended inputs. Differential inputs are not supported in this mode because the PGA must be powered up, and thus, consume more power.

In active mode, energysense audio signal detection on any channels other than the primary is not available; however, other inputs can be read using the secondary ADC channel driven in controlsense mode.

In sleep mode, each input pin can be configured to perform either energysense or controlsense. Both functions can generate interrupts when their thresholds are crossed. All inputs will be cycled through and converted continuously, performing either an enerysense or a controlsense function.

In active mode, any dc based controls will either need to be polled continuously by the systems host, or streamed out continuously in a 6ch TDM mode. In an application, this may mean that the main input is being converted, while the system battery level, or analog volume control knob position is polled using controlsense.

To make the secondary ADC as flexible as possible in both energysense and controlsense modes, the following controls and coefficients are available in the register map. More details on each are in the relevant following sections.

• Coefficients for the secondary ADC low-pass filter
• Coefficients for the secondary ADC high-pass filter
• Reference voltage and interrupt voltage delta for each input in controlsense mode
• Signal loss conditions (time and threshold)
• Signal resume conditions (threshold)
• Interrupt behavior (for example, ping every x ms if host does not clear)
• Scan time for each single ended input

9.3.10.3 Secondary ADC Controlsense DC Level Change Detection

This function is used for external analog controls, such as potentiometers to set volume, tone control, or a sensor. The data for control sense has no high pass filter applied to it, even if the main audio path does have a HPF enabled.

AS shown in Figure 36, there are two parameters for the dc level change detection: reference level (REF_LEVEL) and difference level (DIFF_LEVEL). Each input pin (input 1 through 8) has a different reference and difference level.

Figure 36. DC Detection Function

Users set a reference point, and a difference point. If the voltage at the control point crosses the difference point then an interrupt is driven from the device. This is useful for filtering out noise, as well as reducing the load on the host processor for controls that tend to be set and forget (such as volume).

The data from the secondary ADC can also be streamed out of the device in TDM form and directly from the I²C register map. AUXADC_DATA_CTRL (Page.0 0x58) is used to configure and check the status of the DC detector.

This feature (thresholds and interrupts) is available in both active and sleep modes. In sleep mode, the device automatically scans through each channel designated a controlsense input. In active mode, the scanning will need to be done manually by a host microcontroller by modifying the SEC_ADC_INPUT_SEL (Page.0, 0x0A) register.

Most applications requiring the use of a potentiometer for control can simply use the SIGDET_DC_LEVEL_CHx_x registers to read the 8-bit value. To enable the SIGDET_DC_LEVEL_CHx_x registers to work, then the DC_NOLATCH AUXADC_DATA_CTRL (Page.0, 0x58, B[7]) should be set to 1, and the appropriate input pins should be set to controlsense inputs SIGDET_CH_MODE (Page.0, 0x30)

Direct 16-bit two's compliment reads from the secondary ADC can be done using AUXADC_DATA_CTRL (Page.0, 0x58) includes a latch function that is used to read the data the secondary ADC on demand in 16-bit two's compliment format from registers 0x59 and 0x5A.

Table 17. Energysense States

9.3.11.1 Energysense Signal Loss Flag

The main ADC constantly monitors the input signal level while in ACTIVE mode. Should the input level remain below a register defined threshold (for example –60 dB - Virtual Coefficient 0x2C, programmable through Page 1.) for a register defined amount of time (for example 1 minute - set by SIGDET_LOSS_TIME (Page.0, 0x33) ), an interrupt can be generated.

If the system MCU decides to move to sleep mode, the PCM186x-Q1 can be moved to SLEEP by stopping BCK/LRCK or using PWRDN_CTRL (Page.0, 0x70); see Table 17 for details.

If BCK and LRCK are stopped by the host after the interrupt, the device goes to the sleep state as shown in Figure 37. Otherwise, the interrupt continues for a few seconds, defined by SIGDET_INT_INTVL (Page.0, 0x36) unless the interrupt and timeout counter is reset.

Figure 37. Energysense Signal Loss

In a typical application, the host MCU will note and reset this register multiple times until a system sleep number is hit. For example, a 5-minute signal loss could be implemented by using the default 1-minute timeout on the PCM186x-Q1, and counting five interrupts. An example is shown in Figure 38.

Figure 38. Interrupt Behavior for Signal Loss

Alternatively, the SIGDET_LOSS_TIME (Page.0, 0x33) register in the device can be changed from one minute (default) to five minutes. This timeout is sample rate dependant. The expected sample rate is 48 kHz, but should the system be running at 96 kHz, then the time will be halved. (192 kHz = quarter the register setting).

The duration of the interrupt can also be modified using INT_PLS (Page.0 0x62) to be pulses, or to be a sticky flag, where sticky is defined as the interrupt is on until cleared.

9.3.11.2 Energysense Signal Detect Circuitry

In sleep mode (BCK and LRCK stop, or by register), the PCM186x-Q1 monitors the signal level or dc level change using the secondary ADC. All eight channels are converted one after the other in a circular manner. The scan time is specified with register SIGDET_SCAN_TIME. All eight channels are measured, even if some have the respective interrupt outputs muted. Accuracy and frequency response are a function of scan time. A long scan time allows detection of lower frequency content. The energysense signal wakeup logic is shown Figure 39.

Figure 39. Energysense Signal Wakeup Logic

There is a balance between lowest frequency detectable, and time on that particular channel. There are three options in register SIGDET_INT_INTVL (Page.0 0x36):

• 50-Hz detect (160 ms per channel)
• 100-Hz detect (80 ms per channel)
• 200-Hz detect (40 ms per channel)

9.3.11.2.1 Energysense Threshold Levels for Both Signal Loss and Signal Detect

There are two threshold levels used for Energysense, as shown in Figure 40. One is the loss of signal level, another one is the resume of signal level.

Figure 40. Dual Thresholds for Energysense

As both thresholds are DSP based, their coefficients are stored in virtual coefficient space that is programmed through the device register map.

For example, to change the resume threshold value to –30 dB (0x040C37):

Write 0x00 0x01 ; # change to register page 1

Write 0x02 0x2D ; # write the memory address of resume threshold

Write 0x04 0x04 ; # bit[23:15]

Write 0x05 0x0C ; # bit[15:8]

Write 0x06 0x37 ; # bit[7:0]

Write 0x01 0x01 ; # execute write operation

9.3.11.3 Programming Various Coefficients for Energysense

Programming the DSP coefficients for the energysense secondary ADC is done through the indirect virtual programming registers in Page1. The low-pass filter (LPF) and high-pass filter (HPF) coefficients can be written to flatten out the frequency response, as well as the energysense loss and resume thresholds. Visually, one can imagine the DSP flow as shown in Figure 41.

Figure 41. Energysense Process Flow

To flatten out the response of the secondary ADC, so that all frequencies are detected evenly, write the biquads shown in Table 18 to the virtual DSP memory, using the techniques discussed in the Programming DSP Coefficients on Software-Controlled Devices section.

9.3.12.1 DSP1 Processing Features

9.3.12.2 DSP2 Processing Features

9.3.12.2.1 Digital Mixing Function

This function allows post ADC mixing, as well as ADC + incoming I²S mix. Volume control functionality can be performed prior to outputting the signal to an I²S DAC or Amplifier.

Gain range is from –120 dB to +18 dB (4.20 format). Phase Inversion can be done by performing the two's compliment of the positive gain coefficient. two's compliment can be performed by inverting all bits in the binary coefficient, and adding 1 to the LSB.

As the DSP coefficients are directly written, no soft ramping is available. Use of I²S receive sacrifices two digital mic channels due to pin limitations.

Coefficients are written indirectly to virtual memory addresses using the registers on page 1. Details of the registers are shown in the Register Map section.

A diagram of the digital mixing functionality is shown in Figure 42.

Figure 42. Digital Mixer Functionality

9.3.15.1 DIN Toggle Detection

DIN toggle can be used to trigger from an external PCM audio data source or any other digital data source (such as a IR remote control UART stream) where there is a toggling logic state. (from 0 V to 3.3 V, or vice versa). All GPIO pins support DIN toggle detection, other than GPIO2.

This function is only enabled in sleep mode.

9.3.15.2 Clearing Interrupts

Each Interrupt type has a specific method to clear. When clearing or resetting an interrupt, always remove the source of the interrupt first.

9.3.16.1 Audio Format Selection

Format selection for the PCM1860-Q1 and PCM1861-Q1 is controlled using a hardware pin configuration. There is a choice of left-justified data (known as LJ) or I²S.

On the PCM186x-Q1 software-controlled devices, format selection is done with the registers in I2S_FMT (Page.0 0x0B), which offers additional support for right-justified (RJ) and time division multiplexed (TDM) data for multiple channels.

The PCM186x-Q1 software-controlled devices also offer an additional DOUT pin that can be driven through the GPIO pins. For an example, see the register details at GPIO1_FUNC (Page.0 0x10).

9.3.16.2 Serial Audio Interface Timing Details

Figure 45. Audio Data Format
(LRCK and BCK Work as Inputs in Slave Mode and as Outputs in Master Mode)

9.3.16.3 Digital Audio Output 2 Configuration

The PCM186x-Q1 four-channel software-controlled devices offer an additional DOUT through the use of a GPIO that has its rate synchronized with the primary DOUT. DOUT2 is configured using the digital mixer, shown in Digital Mixing Function. In TDM Modes, DOUT2 is not available.

The GPIO used for DOUT2 can be set using registers. GPIO0 is used for SPI-MOSI in SPI mode, however, it can be retasked for DOUT2 duties if MOSI is not required.GPIO0_FUNC (Page.0 0x10), GPIO1_FUNC (Page.0 0x10), GPIO2_FUNC (Page.0 0x11), or GPIO3_FUNC (Page.0 0x11) can be used to set GPIOx to DOUT2

9.3.16.4 Time Division Multiplex (TDM Support)

The software-controlled devices can support TDM for both slave and master modes. In many devices, this is also known as DSP Mode.

Data on the TDM stream can be between two and four channels of audio content from each PCM186x-Q1 mixer output. By default, each mixer passes data from the respective ADC in a bypass or passthrough configuration. Data from the secondary ADC can also be output on channels five and six. The frame rate in TDM mode fixed to 256 BCK per frame, and the duty cycle of the LRCK (or frame sync signal) can be either a 50 / 50 duty cycle, or a single bit at the start of the frame.

Up to 32 bits per channel are available. In 32-bit mode, 24 bits of data and 8 bits of padding (zero) are used per channel. In 24-, 20-, and 16-bit data, no padding is provided between channels. In 24-bit mode, channel two begins transmitting on bit clock 25.

In data formats lower than 24 bits, the data is simply truncated, not dithered to 16 bits.

In slave mode, only a rising edge on the first bit is required to start the frame. (similar to MSB-first, left-justified).

In master mode, only a 50% duty cycle on the output is possible. This configuration is made by setting TDM_LRCK_MODE (Page.0 0x0B) to 0.

Typically when interfacing to a DSP, only the rising edge on the first bit of data of the frame is required.

While the device is not transmitting data (but still being clocked), the DOUT pin will be Hi-Z (high impedance) to allow other devices on the bus to transmit their data.

TDM mode is configured using I2S_FMT (Page.0 0x0B), TDM_LRCK_MODE (Page.0 0x0B), TDM_OSEL (Page.0 0x0C)

The timing limits for the interface signals are defined by the Serial Audio Data Interface Configuration section with the addition that the BCK period minimum must at least 1 / (512 × f_S) to ensure that data is clocked in correctly.

The audio format is shown below. The 24-bit data can fit up to 10 channels of data in a 256x bitclock stream; however, the I²C-controlled devices only have two possible I²C addresses. The eight channels of audio data should be no issue.

Figure 46. Audio Format for TDM

9.3.16.5 Decimation Filter Select

The PCM186x-Q1 offers a choice of two different digital filters, a Classic FIR response and a low latency IIR.

9.3.16.6 Serial Audio Data Interface Configuration

The PCM186x-Q1 devices interface to the audio system through LRCK, BCK and DOUT.

The PCM186x-Q1 hardware-controlled devices are configured using pin MD4 to select between left-justified data and I²S.

The PCM186x-Q1 software-controlled devices are configured using register I2S_FMT (Page.0 0x0B). Use register I2S_TX_OFFSET (Page.0 0x0D) when dealing with TDM systems to offset the data transmit.

In addition, the offset required for receiving 24-bit data is programmed using RX_TDM_OFFSET (P0, R0x0E).

Table 19. Power Modes

9.4.1.1 PCM1860-Q1 and PCM1861-Q1 Hardware Device Power Down Functions

9.4.1.2 PCM186x-Q1 Software Device Power Down Functions

9.4.1.3 Bypassing the Internal LDO to Reduce Power Consumption

The PCM186x-Q1 has an integrated LDO allowing single 3.3-V supply operation. However, developers desiring to minimize power consumption can bypass the on-chip LDO and provide 1.8 V to IOVDD and to LDO under the following conditions:

• TDM mode is limited to BCK driving a maximum of 25 MHz, because the BCK and DATA cells cannot exceed 25 MHz when IOVDD is 1.8 V. Consequently, a maximum of 96-kHz sampling frequency operation is possible.
• IOVDD MUST be 1.8 V along with LDO, if an external 1.8 V supply is used to bypass the internal LDO.

9.5.1.1 Hardware Control Configuration

PCM186x-Q1 devices require the following functions to be configured on startup. Hardware-controlled devices require a subset of these configurations:

• Control interface type and address for PCM186x-Q1 software-controlled devices
• The clock mode and rate (automatic in slave mode, or divider ratio in master mode) for hardware-controlled devices. For more details see the Clocks section.
• The interface audio data format for hardware-controlled devices.
• Digital filter selection (FIR or IIR) for hardware-controlled devices; requires a power cycle to change.
• Analog input channels and PGA gain for hardware-controlled devices.

9.5.1.2 Software-Controlled Device Configuration

PCM186x-Q1 software-controlled devices are configured and controlled by using either I²C or SPI using MD0 and MD1. Table 20 shows the MD0 control protocols, and Table 21 shows the MD1 mode selection.

9.5.1.3 SPI Interface

The SPI interface is a 4-wire synchronous serial port that operates asynchronously to the serial audio interface and the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers.

The control interface includes MISO, MOSI, MC, and MS. MISO (master in slave out) is the serial data output, used to read back the values of the mode registers; MOSI (master out slave in) is the serial data input, used to program the mode registers.

MC is the serial bit clock, used to shift data in and out of the control port on the MC falling edge. MS is the active-low mode control enable, used to enable the internal mode register access. If data from the device is not required, the MISO pin can be assigned to GPIO1 by register control.

9.5.1.3.1 Register Read and Write Operation

All read and write operations for the serial control port use 16-bit data words. Figure 47 shows the control data word format. The most significant bit is the read and write (R/W) bit. For write operations, the bit must be set to 0. For read operations, the bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or address) for the read and write operations. The least significant eight bits, D[7:0], contain the data to be written to, or the data that was read from, the register specified by IDX[6:0].

Figure 48 and Figure 49 show the functional timing diagram for writing or reading through the serial control port. MS should be held at logic 1 state until a register needs to be written or read. To start the register write or read cycle, MS should be set to logic 0. Sixteen clocks are then provided on MC, corresponding to the 16 bits of the control data word on MOSI and readback data on MISO. After the eighth clock cycle has completed, the data from the indexed-mode control register appears on MISO during the read operation. After the sixteenth clock cycle has completed, the data is latched into the indexed-mode control register during the write operation. To write or read subsequent data, MS should be set to logic 1 once.

NOTE:

B8 is used for selection of write or read. Setting = 0 indicates a write, while = 1 indicates a read. Bits 15–9 are used for register address. Bits 7–0 are used for register data.

Figure 47. Control Data Word Format for MDI

Figure 48. Serial Control Format for Write

Figure 49. Serial Control Format for Read

9.5.1.4 I²C Interface

The PCM186x-Q1 software-controlled devices support the I²C serial bus and the data transmission protocol for standard and fast mode as a slave device. This protocol is explained in I²C specification 2.0.

The I²C control port is available even in the absence of any other clocks in the system.

In I²C mode, the control pins are changed as shown in Table 22.

9.5.1.4.2 Packet Protocol

A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data if write or acknowledge if read, and stop condition. The PCM186x-Q1 software-controlled devices support only slave receivers and slave transmitters. Figure 50 shows the basic I²C framework.

write operation

Transmitter	M	M	M	S	M	S	M	S	------------	S	M
Data Type	St	slave address	R/W	ACK	DATA	ACK	DATA	ACK		ACK	Sp

read operation

Transmitter	M	M	M	S	M	S	M	S	------------	S	M
Data Type	St	slave address	R/W	ACK	DATA	ACK	DATA	ACK		ACK	Sp

	M: Master Device MMM S: Slave Device
	St: Start Condition MMM Sp: Stop Conditiion

Figure 50. Basic I²C Framework

9.5.3.1 Active Mode Flow Diagram

Figure 51. Active Mode Flow Chart

9.5.3.2 Basic Device Configuration

The device by default starts in slave mode at 48 kHz (per the EVM)

Set global loss level to be –50 dB using the DSP coefficient method.

Set 4R as controlsense input (for example, a control voltage for volume control) using SIGDET_CH_MODE (0x30)

Configure active mode secondary to be channel 4R using SEC_ADC_INPUT_SEL (0x0A)

Set Read Data without latch in register AUXADC_DATA_CTRL (0x58)

Set interrupts (energysense and controlsense) using INT_EN (0x60)

Set interrupt pulse for 3 mS (makes it easier to see it visually using INT_PLS (0x62)

9.5.3.3 Clear Energysense Interrupt

Disable the energysense interrupt in INT_STAT register (0x61)

Remove the interrupt source by changing the loss detect threshold to 110 dB (ADC noise level) using the DSP coefficient method.

Write 0xFF to the SIGDET_STAT (0x32) register.

Write 0x00 to the SIGDET_STAT (0x32) register.

Change the loss detect threshold back to –50 dB using the DSP coefficient method.

Re-enable the energysense interrupt in INT_STAT register (0x61)

9.5.3.4 Update System Settings

Read interrupt status INT_STAT register(0x61)

Clear interrupt enable INT_EN (0x60)

Check which input caused the interrupt; in this case, looking for (4R) SIGDET_STAT (0x32)

Read new 4R data (for example, SIGDET_DC_LEVEL_CH4_R 0x57).

Host would normally process as needed. (foe example, change volume in the amplifier)

Set SIGDET_DC_REF_CH4_R (0x55) to be the new value.

Now that interrupt source is removed, we can clear the SIGDET_STAT register (0x32)

Write 0xFF to SIGDET_STAT register (0x32).

Write 0x00 to SIGDET_STAT register (0x32).

Re-enable control Sense Interrupt in INT_EN (0x60)

9.5.3.5 Sleep Mode Flow Diagram

The sleep mode flow chart is shown in Figure 52.

Figure 52. Sleep Mode Flow Chart

9.5.3.6 Update Controlsense values in Sleep Mode

9.5.4.1 Coefficient Data Formats

All mixer gain coefficients are 24-bit coefficients using a 4.20 number format. Numbers formatted as 4.20 numbers have 4 bits to the left of the binary point and 20 bits to the right of the binary point.

The most significant bit of the 4.20 number format is the sine bit. It is used, as part of a two's complement number to invert the phase of that mixer input.

See SLAC663 for a calculator to convert from dB to the hexadecimal coefficient required.

Table 23. Virtual 24-Bit DSP Coefficient Registers