SLES230A September   2008  – August 2015 PCM2912A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
      1. 7.6.1 ADC Digital Decimation Filter Frequency Response
      2. 7.6.2 ADC Digital High-Pass Filter Frequency Response
      3. 7.6.3 ADC Analog Antialiasing Filter Frequency Response
      4. 7.6.4 DAC Digital Interpolation Filter Frequency Response
      5. 7.6.5 DAC Analog FIR Filter Frequency Response
      6. 7.6.6 DAC Analog Low-Pass Filter Frequency Response
      7. 7.6.7 ADC
      8. 7.6.8 DAC
      9. 7.6.9 Supply Current
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Clock and Reset
      2. 9.3.2  DAC
      3. 9.3.3  ADC
      4. 9.3.4  Microphone Bias
      5. 9.3.5  Microphone Amplifier
      6. 9.3.6  Input PGA
      7. 9.3.7  Sidetone Programmable Attenuator
      8. 9.3.8  Output Programmable Attenuator
      9. 9.3.9  VCOM1 and VCCM2
      10. 9.3.10 Filter Pins
      11. 9.3.11 Interface Sequence
        1. 9.3.11.1 Power-On, Attach, and Play Back Sequence
        2. 9.3.11.2 Play, Stop, and Detach Sequence
        3. 9.3.11.3 Record Sequence
        4. 9.3.11.4 Suspend and Resume Sequence
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 USB Interface
        1. 9.5.1.1 Device Configuration
        2. 9.5.1.2 Interface #0
        3. 9.5.1.3 Interface #1
        4. 9.5.1.4 Interface #2
        5. 9.5.1.5 Endpoints
        6. 9.5.1.6 Internal Regulator
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • On-Chip USB Interface:
    • With Full-Speed Transceivers
    • Fully Compliant With USB 2.0 Specification
    • Certified By USB-IF
    • Partially Programmable Descriptors
    • Adaptive Isochronous Transfer for Playback
    • Asynchronous-Isochronous Transfer for Record
    • Bus Powered
  • 16-Bit Delta-Sigma ADC and DAC
  • Sampling Rate:
    • 8, 11.025, 16, 22.05, 32, 44.1, or 48 kHz
  • On-Chip Clock Generator:
    • With Single 6-MHz Clock Source
  • Mono ADC with Microphone Input
    • Analog Performance at VBUS = 5 V:
      • THD+N: 0.01%
      • SNR: 92 dB
      • Dynamic Range: 90 dB
    • Decimation Digital Filter
      • Passband Ripple: ±0.05 dB
      • Stop-Band Attenuation: –65 dB
    • Single-Ended Voltage Input
    • Antialiasing Filter Included
    • Digital HPF Included
    • Microphone Bias, Microphone Amplifier, and Input PGA
  • Stereo DAC With Headphone Output
    • Analog Performance at VBUS = 5.0 V:
      • THD+N: 0.01% (RL > 10 kΩ)
      • THD+N: 0.02% (RL = 32 Ω)
      • SNR: 92 dB
      • Dynamic Range: 90 dB
      • PO: 13 mW (RL = 32 Ω)
      • PO: 25 mW (RL = 16 Ω)
    • Oversampling Digital Filter
      • Passband Ripple: ±0.1 dB
      • Stop-Band Attenuation: –43 dB
      • Single-Ended Voltage Output
      • Analog LPF Included
      • Sidetone PGA, Output PGA, and HP Amplifier
  • Multifunctions:
    • Suspend, Playback, and Record Status Flag
    • Microphone Amplifier, Mute, and Gain Control
  • Pop/Click Noise-Free
  • Single Power-Supply: 5 V Typical (VBUS)
  • Package: 32-Pin TQFP

2 Applications

  • USB Headset
  • USB Headphone
  • USB Speaker
  • USB Featured Consumer Audio Product
  • USB Audio Interface Box
  • USB Monitor
  • Video Conference System

3 Description

The PCM2912A is the Texas Instruments single-chip, USB stereo audio codec with a USB, 2.0-compliant, full-speed protocol controller and an analog front-end (AFE) function for headset applications.

The USB protocol controller works with no software code, but USB descriptors can be modified on request. The PCM2912A employs SpAct™ architecture, TI’s unique system that recovers the audio clock from USB packet data. On-chip analog PLLs with SpAct enables independent playback and record sampling rates with low clock jitters.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
PCM2912A TQFP (32) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

PCM2912A Block_Diagram.gif

4 Revision History

Changes from * Revision (September 2008) to A Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, Device Comparison table, and Mechanical, Packaging, and Orderable Information section Go