SLAS724A September   2008  – November 2014 PCM3070

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  Handling Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics, ADC
    6. 8.6  Electrical Characteristics, Bypass Outputs
    7. 8.7  Electrical Characteristics, Audio DAC Outputs
    8. 8.8  Electrical Characteristics, LDO
    9. 8.9  Electrical Characteristics, Misc.
    10. 8.10 Electrical Characteristics, Logic Levels
    11. 8.11 I2S LJF and RJF Timing in Master Mode (see )
    12. 8.12 I2S LJF and RJF Timing in Slave Mode (see )
    13. 8.13 DSP Timing in Master Mode (see )
    14. 8.14 DSP Timing in Slave Mode (see )
    15. 8.15 I2C Interface Timing
    16. 8.16 SPI Interface Timing (See )
    17. 8.17 Typical Characteristics
      1. 8.17.1 Typical Performance
      2. 8.17.2 Typical Characteristics, FFT
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Device Connections
        1. 10.3.1.1 Digital Pins
          1. 10.3.1.1.1 Multifunction Pins
        2. 10.3.1.2 Analog Pins
      2. 10.3.2 Analog Audio I/O
        1. 10.3.2.1 Analog Bypass
        2. 10.3.2.2 ADC Bypass Using Mixer Amplifiers
        3. 10.3.2.3 Headphone Output
        4. 10.3.2.4 Line Outputs
      3. 10.3.3 ADC
        1. 10.3.3.1 ADC Processing
          1. 10.3.3.1.1 ADC Processing Blocks
      4. 10.3.4 DAC
        1. 10.3.4.1 DAC Processing Blocks — Overview
      5. 10.3.5 Digital Audio IO Interface
      6. 10.3.6 Clock Generation and PLL
      7. 10.3.7 Control Interfaces
        1. 10.3.7.1 I2C Control
        2. 10.3.7.2 SPI Control
    4. 10.4 Device Functional Modes
      1. 10.4.1 MiniDSP
      2. 10.4.2 Software
    5. 10.5 Register Map
      1. 10.5.1 Register Map Summary
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 Reference Filtering Capacitor
      2. 11.2.2 Detailed Design Procedures
        1. 11.2.2.1 Analog Input Connection
        2. 11.2.2.2 Analog Output Connection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
    4. 14.4 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

This document describes signals that take on different names depending on how they are configured. In such cases, the different names are placed together and separated by slash (/) characters. For example, "SCL/SS". Active low signals are represented by overbars.

QFN Package
(Bottom View)
rhb_po_las724.gif

Pin Functions

PIN NAME TYPE(1) DESCRIPTION
1 MCLK DI Master Clock Input
2 BCLK DIO Audio serial data bus (primary) bit clock
3 WCLK DIO Audio serial data bus (primary) word clock
4 DIN DI Primary function:
Audio serial data bus data input
MFP1 Secondary function:
General Purpose Clock Input
General Purpose Input
5 DOUT DO Primary function:
Audio serial data bus data output
MFP2 Secondary function:
General Purpose Output
Clock Output
INT1 Output
INT2 Output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
6 IOVDD Power IO voltage supply 1.1V – 3.6V
7 IOVSS Ground IO ground supply
8 SCLK DI Primary function: (SPI_Select = 1)
/ SPI serial clock
MFP3 Secondary function: (SPI_Select = 0)
Audio serial data bus (secondary) bit clock input
Audio serial data bus (secondary) DAC or common word clock input
Audio serial data bus (secondary) ADC word clock input
Audio serial data bus (secondary) data input
General Purpose Input
9 SCL/SS DI I2C interface serial clock (SPI_Select = 0)
SPI interface mode chip-select signal (SPI_Select = 1)
10 SDA/MOSI DI I2C interface mode serial data input (SPI_Select = 0)
SPI interface mode serial data input (SPI_Select = 1)
11 MISO DO Primary function: (SPI_Select = 1)
/ Serial data output
MFP4 Secondary function: (SPI_Select = 0)
General purpose output
CLKOUT output
INT1 output
INT2 output
Audio serial data bus (primary) ADC word clock output
Audio serial data bus (secondary) data output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
12 SPI_ SELECT DI Control mode select pin ( 1 = SPI, 0 = I2C )
13 IN1_L AI Multifunction Analog Input,
or Single-ended configuration: Line 1 left
or Differential configuration: Line right, negative
14 IN1_R AI Multifunction Analog Input,
or Single-ended configuration: or Line 1 right
or Differential configuration: Line right, positive
15 IN2_L AI Multifunction Analog Input,
or Single-ended configuration: Line 2 left
or Differential configuration: Line left, positive
16 IN2_R AI Multifunction Analog Input,
or Single-ended configuration: Line 2 right
or Differential configuration: Line left, negative
17 AVSS Ground Analog ground supply
18 REF AO Reference voltage output for filtering
19 NC -- NC, do not connect
20 IN3_L AI Multifunction Analog Input,
or Single-ended configuration: Line 3 left,
or Differential configuration: Line left, positive,
or Differential configuration: Line right, negative
21 IN3_R AI Multifunction Analog Input,
or Single-ended configuration: Line 3 right,
or Differential configuration: Line left, negative,
or Differential configuration: Line right, positive
22 LOL AO Left line output
23 LOR AO Right line output
24 AVDD Power Analog voltage supply 1.5V–1.95V
Input when A-LDO disabled,
Filtering output when A-LDO enabled
25 HPL AO Left high power output driver
26 LDOIN/HPVDD Power LDO Input supply and Headphone Power supply 1.9V– 3.6V
27 HPR AO Right high power output driver
28 DVSS Ground Digital Ground and Chip-substrate
29 DVDD Power If LDO_SELECT Pin = 0 (D-LDO disabled)
Digital voltage supply 1.26V – 1.95V
 If LDO_SELECT Pin = 1 (D-LDO enabled)
Digital voltage supply filtering output
30 LDO_ SELECT DI D-LDO enable signal (1 = D-LDO enable, 0 = D-LDO disabled)
31 RESET DI Reset (active low)
32 GPIO DI Primary function:
General Purpose digital IO
MFP5 Secondary function:
CLKOUT Output
INT1 Output
INT2 Output
Audio serial data bus ADC word clock output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
Thermal Pad Thermal Pad N/A Connect to PCB ground plane. Not internally connected.
(1) DI (Digital Input), DO (Digital Output), DIO (Digital Input/Output), AI (Analog Input), AO (Analog Output), AIO (Analog Input/Output)