SBAS884A March 2020 – June 2020 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1
PRODUCTION DATA.
This register is the clock source configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIS_PLL_SLV_CLK_SRC | MCLK_FREQ_SEL_MODE | MCLK_RATIO_SEL[2:0] | Reserved | ||||
RW-0h | RW-0h | RW-2h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DIS_PLL_SLV_CLK_SRC | RW | 0h | Audio root clock source setting when the device is configured with the PLL disabled in the auto clock configuration for slave mode (AUTO_MODE_PLL_DIS = 1).
0d = BCLK is used as the audio root clock source 1d = MCLK (GPIOx or GPIx) is used as the audio root clock source (the MCLK to FSYNC ratio is as per MCLK_RATIO_SEL setting) |
6 | MCLK_FREQ_SEL_MODE | RW | 0h | Master mode MCLK (GPIOx or GPIx) frequency selection mode (valid when the device is in auto clock configuration).
0d = MCLK frequency is based on the MCLK_FREQ_SEL (P0_R19) configuration 1d = MCLK frequency is specified as a multiple of FSYNC in the MCLK_RATIO_SEL (P0_R22) configuration |
5-3 | MCLK_RATIO_SEL[2:0] | RW | 2h | These bits select the MCLK (GPIOx or GPIx) to FSYNC ratio for master mode or when MCLK is used as the audio root clock source in slave mode.
0d = Ratio of 64 1d = Ratio of 256 2d = Ratio of 384 3d = Ratio of 512 4d = Ratio of 768 5d = Ratio of 1024 6d = Ratio of 1536 7d = Ratio of 2304 |
2-0 | Reserved | R | 0h | Reserved |