8.2.1.1 Design Requirements
There are only a few requirements to take into account when using the PGA305 device in a design:
- Do not exceed the maximum slew rate of 0.5 V/µs at the PWR pin.
- Place a 100-nF capacitor from the AVDD pin to ground, as close to the AVDD pin as possible.
- Place a 100-nF capacitor from the DVDD pin to ground, as close to the DVDD pin as possible.
- Place a capacitor between 10 nF and 1000 nF from the REFCAP pin to ground as close to the REFCAP pin as possible.
- Place a 150-Ω resistor between the COMP pin and the emitter of the BJT for current-loop stability purposes.
- Place a 10-Ω resistor between the FB+ pin and the negative terminal of the controller for current measurement.