SLDS231
August 2018
PGA305
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
PAG305 Simplified Block Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics – Reverse Voltage Protection
6.6
Electrical Characteristics – Regulators
6.7
Electrical Characteristics – Internal Reference
6.8
Electrical Characteristics – Bridge Sensor Supply
6.9
Electrical Characteristics – Temperature Sensor Supply
6.10
Electrical Characteristics – Internal Temperature Sensor
6.11
Electrical Characteristics – P Gain (Chopper Stabilized)
6.12
Electrical Characteristics – P Analog-to-Digital Converter
6.13
Electrical Characteristics – T Gain (Chopper Stabilized)
6.14
Electrical Characteristics – T Analog-to-Digital Converter
6.15
Electrical Characteristics – One-Wire Interface
6.16
I2C Interface
6.17
Electrical Characteristics – DAC Output
6.18
Electrical Characteristics – DAC Gain
6.19
Electrical Characteristics – Non-Volatile Memory
6.20
Electrical Characteristics – Diagnostics
6.21
Operating Characteristics
6.22
I2C Interface Timing Requirements
6.23
Timing Diagram
6.24
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Reverse-Voltage Protection Block
7.3.2
Linear Regulators
7.3.3
Internal Reference
7.3.3.1
High-Voltage Reference
7.3.3.2
Accurate Reference
7.3.4
BRG+ to BRG– Supply for the Resistive Bridge
7.3.5
ITEMP Supply for the Temperature Sensor
7.3.6
Internal Temperature Sensor
7.3.7
P Gain
7.3.8
P Analog-to-Digital Converter
7.3.8.1
P Sigma-Delta Modulator for P ADC
7.3.8.2
P Decimation Filter for P ADC
7.3.9
T Gain
7.3.10
T Analog-to-Digital Converter
7.3.10.1
T Sigma-Delta Modulator for T ADC
7.3.10.2
T Decimation Filters for T ADC
7.3.11
P GAIN and T GAIN Calibration
7.3.12
One-Wire Interface (OWI)
7.3.12.1
Overview of OWI
7.3.12.2
Activating and Deactivating the OWI Interface
7.3.12.2.1
Activating OWI Communication
7.3.12.2.2
Deactivating OWI Communication
7.3.12.3
OWI Protocol
7.3.12.3.1
OWI Frame Structure
7.3.12.3.1.1
Standard Field Structure
7.3.12.3.1.2
Frame Structure
7.3.12.3.1.3
Sync Field
7.3.12.3.1.4
Command Field
7.3.12.3.1.5
Data Fields
7.3.12.3.2
OWI Commands
7.3.12.3.2.1
OWI Write Command
7.3.12.3.2.2
OWI Read Initialization Command
7.3.12.3.2.3
OWI Read-Response Command
7.3.12.3.2.4
OWI Burst-Write Command (EEPROM Cache Access)
7.3.12.3.2.5
OWI Burst Read Command (EEPROM Cache Access)
7.3.12.3.3
OWI Operations
7.3.12.3.3.1
Write Operation
7.3.12.3.3.2
Read Operation
7.3.12.3.3.3
EEPROM Burst Write
7.3.12.3.3.4
EEPROM Burst Read
7.3.12.4
OWI Communication-Error Status
7.3.13
I2C Interface
7.3.13.1
Overview of I2C Interface
7.3.13.2
Clocking Details of I2C Interface
7.3.13.3
I2C Interface Protocol
7.3.13.4
PGA305 I2C Runtime Commands
7.3.13.5
PGA305 I2C Transfer Example
7.3.14
DAC Output
7.3.14.1
Ratiometric vs Absolute
7.3.15
DAC Gain
7.3.16
Memory
7.3.16.1
EEPROM Memory
7.3.16.1.1
EEPROM Cache
7.3.16.1.2
EEPROM Programming Procedure
7.3.16.1.3
EEPROM Programming Current
7.3.16.1.4
CRC
7.3.16.2
Control and Status Registers Memory
7.3.17
Diagnostics
7.3.17.1
Power Supply Diagnostics
7.3.17.2
Signal Chain Faults
7.3.17.2.1
P Gain and T Gain Input Faults
7.3.17.2.2
P Gain and T Gain Output Diagnostics
7.3.17.2.3
Masking Signal Chain Faults
7.3.17.2.4
Fault Detection Timing
7.3.18
Reading Diagnostics Information Through I2C
7.3.19
Digital Compensation and Filter
7.3.19.1
Digital Gain and Offset
7.3.19.2
TC and NL Correction
7.3.19.2.1
TC and NL Coefficients
7.3.19.2.1.1
No TC and NL Coefficients
7.3.19.2.2
TC Compensation Using the Internal Temperature Sensor
7.3.19.3
Clamping
7.3.19.4
Filter
7.3.20
Filter Coefficients
7.3.20.1
No Filtering
7.3.20.2
Filter Coefficients for P ADC Sampling Rate = 1024 µs
7.4
Device Functional Modes
7.4.1
Voltage Mode
7.4.2
Current Mode
7.5
Register Maps
7.5.1
Register Settings
7.5.2
Control and Status Registers
7.5.2.1
Digital Interface Control (M0 Address = 0x40000506) (DI Page Address = 0x2) (DI Page Offset = 0x06)
7.5.2.2
DAC_CTRL_STATUS (M0 Address: 0x40000538) (DI Page Address: 0x2) (DI Page Offset: 0x38)
7.5.2.3
DAC_CONFIG (EEPROM Address = 0x40000032) (DI Page Address: 0x2) (DI Page Offset: 0x39)
7.5.2.4
OP_STAGE_CTRL (EEPROM Address = 0x40000033) (DI Page Address: 0x2) (DI Page Offset: 0x3B)
7.5.2.5
BRDG_CTRL (EEPROM Address = 0x40000034) (DI Page Address: 0x2) (DI Page Offset: 0x46)
7.5.2.6
P_GAIN_SELECT (EEPROM Address = 0x40000035) (DI Page Address: 0x2) (DI Page Offset: 0x47)
7.5.2.7
T_GAIN_SELECT (EEPROM Address = 0x40000036) (DI Page Address: 0x2) (DI Page Offset: 0x48)
7.5.2.8
TEMP_CTRL (EEPROM Address = 0x40000037) (DI Page Address: 0x2) (DI Page Offset: 0x4C)
7.5.2.9
TEMP_SE (EEPROM Address = 0x4000003A)
7.5.2.10
DIAG_ENABLE (EEPROM Address = 0x40000056)
7.5.2.11
EEPROM_LOCK (EEPROM Address = 0x40000057)
7.5.2.12
AFEDIAG_CFG (EEPROM Address = 0x40000058)
7.5.2.13
AFEDIAG_MASK (EEPROM Address = 0x40000059)
7.5.2.14
ADC_24BIT_ENABLE (EEPROM Address = 0x40000068)
7.5.2.15
OFFSET_ENABLE (EEPROM Address = 0x40000069)
7.5.2.16
COMPENSATION_CONTROL (EEPROM Address = N/A) (DI Page Address: 0x0) (DI Page Offset: 0x0C)
7.5.2.17
EEPROM_PAGE_ADDRESS (EEPROM Address = N/A) (DI Page Address: 0x5) (DI Page Offset: 0x88)
7.5.2.18
EEPROM_CTRL (EEPROM Address = N/A) (DI Page Address: 0x5) (DI Page Offset: 0x89)
7.5.2.19
EEPROM_CRC (EEPROM Address = N/A) (DI Page Address: 0x5) (DI Page Offset: 0x8A)
7.5.2.20
EEPROM_STATUS (EEPROM Address = N/A) (DI Page Address: 0x5) (DI Page Offset: 0x8B)
7.5.2.21
EEPROM_CRC_STATUS (EEPROM Address = N/A) (DI Page Address: 0x5) (DI Page Offset: 0x8C)
7.5.2.22
EEPROM_CRC_VALUE (EEPROM Address = 0x4000007F) (DI Page Address: 0x5) (DI Page Offset: 0x8D)
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
4-mA to 20-mA Output With Internal Sense Resistor
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Calibration Tips
8.2.1.2.1.1
Programming the EEPROM for 4-mA to 20-mA Output
8.2.1.3
Application Curve
8.2.2
0- to 10-V Absolute Output With Internal Drive
8.2.2.1
Design Requirements
8.2.3
0- to 5-V Ratiometric Output With Internal Drive
8.2.3.1
Design Requirements
8.2.3.2
Detailed Design Procedure
8.2.3.2.1
Programmer Tips
8.2.3.2.1.1
Resetting the Microprocessor and Enable Digital Interface
8.2.3.2.1.2
Turning On the Accurate Reference Buffer (REFCAP Voltage)
8.2.3.2.1.3
Turning On DAC and DAC GAIN
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Receiving Notification of Documentation Updates
11.2
Community Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RHH|36
MPQF144E
Thermal pad, mechanical data (Package|Pins)
RHH|36
QFND460A
Orderable Information
slds231_oa
slds231_pm
8.2.3.2
Detailed Design Procedure