SLDS231 August 2018 PGA305
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Gain steps (2 bits) | Gain control bits = 0b00 at dc | 1.33 | V/V | |||
Gain control bits = 0b01 | 2 | |||||
Gain control bits = 0b10 | 5 | |||||
Gain control bits = 0b11 | 20 | |||||
Gain bandwidth product | 350 | kHz | ||||
Noise density(1) | f = 0.1 Hz to 100 Hz
at gain = 5 V/V, across temperature |
110 | nV/√Hz | |||
Input offset voltage | 95 | µV | ||||
Input bias current | 5 | nA | ||||
Frequency response | Gain = 20 V/V, <100 Hz | 0.335 | %V/V | |||
Common mode voltage range | Depends on selected gain and current supply(2) | |||||
Common-mode rejection ratio | fCM = 50 Hz | 110 | dB | |||
Input impedance | 1 | MΩ |