SLDS231 August 2018 PGA305
PRODUCTION DATA.
Figure 51 shows how the main guidelines listed in these layout guidelines can be implemented in a six-layer, socketed EVM of the PGA305 device. Two main GND planes (layer 2 and 5) were used to provide a nearby GND plane to each of the signal layers and the power plane (layer 3) in the EVM. This EVM supports voltage and current modes for the device, so depending on the application, GND separation may be necessary as a result. For this example, layer 2 is a solid GND plane for the majority of the circuitry in the EVM (IRETURN). Most of the circuitry is referred to this GND plane, so layers 3 and 4 also contain copper pours connected to IRETURN. This GND plane is the return path for the supply used in the 4-mA to 20-mA loop. Layer 5 is a split plane for the ground references for the digital communication signals used for this EVM (USBGND) and the ground pins in the device (GND, AVSS and DVSS), referred to as ASICGND. The EVM provides jumpers to connect, or disconnect, these three planes one from another, depending on the desired configuration.
Figure 51 shows the recommended capacitors for the proper operation of the PGA305 device. These capacitors are placed as close to their respective pins of the socket used for this particular EVM as possible. The signal traces for FB–, FB+, COMP, and OUT are also routed in the same layer to avoid crossing each other and to minimize coupling.