SBOSAG3 March   2024 PGA849

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gain Control
      2. 7.3.2 Input Protection
      3. 7.3.3 Using the Output Difference Amplifier to Shape Noise
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 ADS8860 16-Bit, 1MSPS, Single-Ended Input, SAR ADC Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2 Detailed Design Procedure

The first filter located at the input of the PGA (see Figure 8-1) helps reduce electromagnetic interference (EMI) and radio frequency interference (RFI), high-frequency, extrinsic noise. This filter can be customized per the application bandwidth and antialiasing requirements.

The second filter is provided by CFB in parallel with the PGA 5kΩ feedback resistors. The PGA resistors are ±15% absolute tolerance, as such, consider the effect of the tolerance on the filter cutoff frequency. CFB = 100pF results in a filter cutoff frequency of 318kHz. On the high side of the resistor tolerance, the filter frequency changes to 277kHz. The device allows for the flexibility to modify the CFB capacitor value to adjust bandwidth, with a trade-off on the broadband noise of the circuit.

The third filter placed at the ADS8860 inputs works as a charge reservoir filter to drive the SAR. The charge kickback filter reduces the instantaneous charge demand of the amplifier, maintaining low distortion that otherwise can degrade because of incomplete ADC sample-and-hold settling. The RC filter combination (RFIL, CDIFF) is tuned for ADC sample-and-hold settling and total harmonic distortion (THD) performance, while maintaining stability of the PGA. High-grade C0G capacitors are used everywhere in the signal path for the low distortion properties.

The PGA849 front-end, accounting for all three filters, provides a nominal f–3dB bandwidth of 310kHz. On the high side of the internal 5kΩ feedback resistor tolerance, the PGA849 f–3dB bandwidth changes to 271kHz and the circuit maintains –0.1dB flatness to 41kHz.

The ADS8860 requires a full-scale input in the range of 0V to the 5V ADC reference. The PGA849 REF pin is set to a nominal voltage of 2.5V to shift the signal to the ADC midscale voltage.

The PGA849 REF voltage is generated by feeding the REF6250 5V reference through a 10kΩ-to-10kΩ precision voltage divider implemented with ±0.05% tolerance, low-drift ±5ppm/°C resistors. Drive the PGA849 REF pin with a low-impedance source, and use the OPA192 as a buffer to drive the REF pin.

The OPA192 buffer is configured in a dual-feedback configuration to provide stability while driving the REF pin and 22nF bypass capacitor. RISO is a 20Ω isolation resistor that provides separation of two feedback paths for optimized stability. Feedback path number one is through feedback resistor, RF = 2kΩ, connected directly to the REF pin. Feedback path number two is through feedback capacitor CF = 2nF connected to the output of the op amp. The circuit provides a loop gain phase margin of 86°. The noninverting input of the OPA192 buffer has a low-pass filter with R = 1kΩ, C = 10nF to reduce the resistive divider thermal noise. Using any other load capacitance requires recalculation of the stability components: RF, CF, and RISO. If modifying the REF bypass capacitance, verify the circuit is stable with simulation using the OPA192 TINA-TI™ SPICE model, and confirm the circuit provides more than 60° of phase margin.