SBOSAG3A March   2024  – December 2024 PGA849

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gain Control
      2. 7.3.2 Input Protection
      3. 7.3.3 Using the Output Difference Amplifier to Shape Noise
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Linear Operating Input Range
      2. 8.1.2 Current Consumption with Differential Inputs
    2. 8.2 Typical Applications
      1. 8.2.1 Driving a Single-Ended Input SAR ADC
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at TA = 25 °C, VS = VSOUT = ±15V, VICM = 0V, VREF = 0V, RL = 10kΩ connected to ground, and G = 1V/V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOS Offset voltage (RTI) G = 1 to 16 ±50 ±350 µV
G < 1 ±50/G ±350/G
Offset voltage drift (RTI) G = 1 to 16, TA = –40°C to +125°C ±0.2 ±1.0 µV/°C
G < 1, TA = –40°C to +125°C ±0.2/G ±1.0/G
PSRR Power-supply rejection ratio ±4V ≤ VS ≤ ±18V, RTI G = 0.125 95 110 dB
G = 0.25 98 114 dB
G = 0.5 100 118
G = 1 120 134
G = 2 120 126
G = 4 120 132
G = 8 120 136
G = 16 120 140
zid Differential input impedance 1 || 1 GΩ || pF
zic Common-mode input impedance 1 || 7 GΩ || pF
VICM Common-mode input voltage VS = ±4V to ±18V (VS–) + 2.5 (VS+) – 2 V
VS = ±4V to ±18V, TA = –40°C to +125°C (VS–) + 3 (VS+) – 2.5
CMRR Common-mode rejection ratio At DC to 60Hz,
VICM = ±10V,
TA = –40°C to +125°C,
RTI		 G = 0.125 64 82 dB
G = 0.25 70 88
G = 0.5 76 94
G = 1 82 100
G = 2 88 106
G = 4 94 112
G = 8 100 118
G = 16 106 124
BIAS CURRENT
IB Input bias current ±0.5 ±1.8 nA
TA = –40°C to +125°C ±1
Input bias current drift TA = –40°C to +125°C ±10 pA/°C
IOS Input offset current ±0.5 ±1 nA
TA = –40°C to +125°C ±1
Input offset current drift TA = –40°C to +125°C ±10 pA/°C
NOISE VOLTAGE
eNI Voltage noise density (RTI) f = 1kHz G = 16 8.6 nV/√Hz
G = 8 8.8
G = 4 9.6
G = 2 13.5
G = 1 23.8
G = 0.5 47.4
G = 0.25 94.9
G = 0.125 186.3
ENI Voltage noise (RTI) fB = 0.1Hz to 10Hz G = 16 0.28 µVPP
G = 8 0.29
G = 4 0.33
G = 2 0.49
G = 1 0.91
G = 0.5 1.82
G = 0.25 3.59
G = 0.125 7.28
iN Input current noise density f = 1kHz 0.3 pA/√Hz
IN Input current noise fB = 0.1Hz to 10Hz 13 pAPP
GAIN
Gain range 0.125 16 V/V
GE Gain error G = 0.125 ±0.010 ±0.045 %
G = 0.25 ±0.005 ±0.030 %
G = 0.5 ±0.005 ±0.030 %
G = 1 ±0.005 ±0.015 %
G = 2 ±0.010 ±0.030 %
G = 4 ±0.015 ±0.040 %
G = 8 ±0.015 ±0.040 %
G = 16 ±0.030 ±0.070 %
Gain nonlinearity G = 0.125 to 16, VOUT > ±5V 2 5 ppm
Gain drift G = 0.125 to 16, TA = –40°C to +125°C ±1 ±2 ppm/°C
OUTPUT
VOUT Output voltage No load VSOUT = ±2.25V VLVSS + 0.1 VLVDD – 0.1 V
RL = 10kΩ VSOUT = ±2.25V VLVSS + 0.2 VLVDD – 0.2
VSOUT = ±18V VLVSS + 0.4 VLVDD – 0.4
CL Load capacitance  Stable operation for capacitive load 100 pF
ISC Short-circuit current Continuous to VSOUT / 2 ±45 mA
TA = –40°C to +125°C ±20 ±60
FREQUENCY RESPONSE
BW Bandwidth, –3dB G = 0.125 to 16 10 MHz
SR Slew rate G ≥ 0.5, VOUT = 10 35 V/µs
G = 0.25, VOUT = 5 23 V/µs
G = 0.125, VOUT = 2.5 10 V/µs
tS Settling time G = 0.125 to 16
VINDIFF = 10V step or VOUT = 10V step		 To 0.01% 0.7 µs
To 0.0015% 0.95
Gain switching time 2 µs
THD+N Total harmonic distortion and Noise Differential input, f = 10kHz, VOUT = 10VPP –110 dB
Single-ended input, f = 10kHz, VOUT = 10VPP –105
HD2 Second-order harmonic distortion Differential input, f = 10kHz, VOUT = 10VPP –120
Single-ended input, f = 10kHz, VOUT = 10VPP –110
HD3 Third-order harmonic distortion Differential input, f = 10kHz, VOUT = 10VPP –120
Single-ended input, f = 10kHz, VOUT = 10VPP –110
REFERENCE INPUT
RIN Reference input impedance 10 kΩ
Reference input current VIN = 0V 140 µA
Reference input voltage VLVSS VLVDD V
Reference gain to output 1 V/V
Reference gain error VOUT = ±10V, inside the voltage swing range 0.01 0.05 %
INPUT STAGE POWER SUPPLY
IQ_input Input stage quiescent current
VS+, VS–		 VIN = 0V 3 3.7 mA
TA = –40°C to +125°C 4.6
OUTPUT STAGE POWER SUPPLY
IQ_output Output stage quiescent current
LVDD, LVSS		 VIN = 0V, VREF = 0V 2.3 2.8 mA
TA = –40°C to 125°C 3.5
DIGITAL LOGIC
VIL Digital input logic low A0, A1, A2 pins, referred to DGND VDGND VDGND + 0.8 V
VIH Digital input logic high A0, A1, A2 pins, referred to DGND VDGND + 1.8 VS+ V
Digital input pin current A0, A1, A2 pins 1.5 3 µA
VDGND DGND voltage VS– (VS+) – 4 V
DGND reference current 4 10 µA