SBOSAG3 March 2024 PGA849
ADVANCE INFORMATION
Refer to the PDF data sheet for device specific package drawings
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VS | Supply voltage on VS+, VS– pins; VS = (VS+) – (VS–) | 0 | 40 | V | |
VSOUT | Supply voltage on LVDD, LVSS pins; VSOUT = VLVDD – VLVSS | 0 | 40 | V | |
Voltage on power pins LVDD, LVSS | (VS–) – 0.5 | (VS+) + 0.5 | V | ||
VIN | Voltage on signal-input pins IN+, IN– | (VS–) – 40 | (VS+) + 40 | V | |
DGND, DA_IN+, DA_IN– pin voltage | (VS–) – 0.5 | (VS+) + 0.5 | V | ||
Voltage on gain-select pins A2, A1, A0 | VDGND – 0.5 | (VS+) + 0.5 | V | ||
VO | Signal output pin maximum voltage | VLVSS – 0.5 | VLVDD + 0.5 | V | |
VREF | Reference input voltage | VLVSS – 0.5 | VLVDD + 0.5 | V | |
IO | Signal-output pins current | –100 | 100 | mA | |
ISC | Output short-circuit current(2) | Continuous | |||
TA | Operating temperature | –50 | 150 | °C |