SLPS755A October   2023  – December 2023 RES11A-Q1

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 AEC-Q200 Qualification Testing
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 DC Measurement Configurations
    2. 6.2 AC Measurement Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Ratiometric Matching
      2. 7.3.2 Ratiometric Drift
      3. 7.3.3 Predictable Voltage Coefficient
      4. 7.3.4 Ultra-Low Noise
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Discrete Difference Amplifier
        1. 8.1.1.1 Difference-Amplifier Common-Mode Rejection Analysis
      2. 8.1.2 Discrete Instrumentation Amplifiers
        1. 8.1.2.1 Instrumentation Amplifier Common-Mode Rejection Analysis
      3. 8.1.3 Fully Differential Amplifier
    2. 8.2 Typical Application
      1. 8.2.1 Common-Mode Shifting Input Stage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 9.1.1.3 TI Reference Designs
        4. 9.1.1.4 Filter Design Tool
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDF|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1 Common-Mode Shifting Input Stage

The RES11A-Q1 can be used to implement a common-mode attenuator at the high-impedance inputs of an instrumentation amplifier (INA). This configuration extends the usable signal range, so long as the maximum differential voltage limitation of each resistor divider is respected.

Figure 8-6 shows an example of a high-side current-sense circuit where a differential voltage, VSHUNT, develops across a sense resistor with an undesirably high common-mode voltage VCM. VREF is used to shift input common-mode voltages VMID1 and VMID2 to levels within the specified input common-mode range of the INA. The amplifier output, VOUT, is a scaled function of VSHUNT, such that nominally:

Equation 28. V O U T = V SHUNT × R IN R G + R I N + R EQUIV

VOUT can be gained up further by the INA stage, to make maximal use of the effective resolution of a downstream ADC. In practice REQUIV is optional; however, if REQUIV = RSHUNT, this resistance equalizes the nominal impedance between VCM and each of the INA high-impedance inputs, thus improving CMRR performance. Select an INA with input bias currents IB1 and IB2 << ISTATIC1 and ISTATIC2, such as the INA333 or INA823. Select a RES11A-Q1 device with a sufficiently high divider series resistance so that ISTATIC1 and ISTATIC2 << ILOAD.

GUID-20220829-SS0I-MBH4-29BL-LNHQHHZFWSJS-low.svg Figure 8-6 RES11A-Q1 Common-Mode Shifting Circuit

To achieve a desired nominal input common-mode voltage, VMID1TARGET, set VREF as follows:

Equation 29. V R E F = V MID1TARGET × R G + R I N + R EQUIV R G + R EQUIV − V CM × R G + R I N + R EQUIV R G + R EQUIV −1