SLPS764 September   2024 RES60A-Q1

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Ratiometric Matching
      2. 6.3.2 Ultra-Low Noise
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Battery Stack Measurement
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 8.1.1.3 TI Reference Designs
        4. 8.1.1.4 Analog Filter Designer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWV|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Ratiometric Matching

The resistors of the RES60A-Q1 are described by the following two equations:

Equation 1. R HV = R HVnom × t abs = R HVnom × t RHV × t SiCr
Equation 2. R LV = R LVnom × t RLV × t SiCr

where

  • RHVnom and RLVnom are the nominal values of each resistor.
  • tabs is an error term that describes the absolute tolerance of the resistors of the RES60A-Q1, such that |tabs| ≤ 15%.
  • tSiCr is the variation in the SiCr resistivity for a wafer, and dominates the absolute tolerance for a given resistor. The two resistors of a given RES60A-Q1 are interdigitated and come from the same area of the wafer; therefore, tSiCr is effectively the same for both of the two resistors, although tSiCr varies on a part-to-part basis. When the divider is considered in ratiometric terms, these error terms drop out; see the following equations.
  • tRHV and tRLV are localized per-resistor variation or offset error terms. These terms describe the remaining effective tolerances of the respective resistors for a given RES60A-Q1 device, after accounting for the universal tSiCr.
Equation 3. R HV R LV = R HVnom × t RHV × t SiCr R LVnom × t RLV × t SiCr = R HVnom × t RHV R LVnom × t RLV = G nom × t RHV t RLV = G
Equation 4. R HV R LV + R HV = R HVnom × t RHV × t SiCr R LVnom × t RLV × t SiCr + R HVnom × t RHV × t SiCr = R HVnom × t RHV R LVnom × t RLV + R HVnom × t RHV

The RES60A-Q1 is specified with a maximum initial divider ratio tolerance of 0.1%, meaning that the relationship between the actual divider ratio, G, and the nominal ratio, Gnom, of a given divider is described by the following:

Equation 5. G = G nom × t D

such that tD0.1%. Because any devices that do not meet these criteria are screened out at final test, these equations can be used with the previous equations to prove the effective bounds of tRHV and tRLV. Therefore, despite the device absolute end-to-end tolerance bounds of ±15%, the effective error tolerances of each resistor (for ratiometric applications) are within approximately ±0.05%, for the worst-case tRHV and tRlV.