SLPS764 September   2024 RES60A-Q1

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Ratiometric Matching
      2. 6.3.2 Ultra-Low Noise
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Battery Stack Measurement
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 8.1.1.3 TI Reference Designs
        4. 8.1.1.4 Analog Filter Designer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWV|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:

  • Reduce parasitic coupling by running sensitive traces, such as the MID connection, as far away from supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
  • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
  • Make sure supply voltages are adequately filtered.
  • Power dissipated in the RES60A-Q1 causes the junction temperature to rise. For reliable operation, junction temperature must be limited to 150°C, maximum. Maintaining a lower junction temperature results in higher reliability.
    • Package thermal resistance, RθJA, is affected by mounting techniques and environments. Poor air circulation can significantly increase thermal resistance to the ambient environment. Best thermal performance is achieved by soldering the RES60A-Q1 onto a circuit board with wide printed circuit traces, especially for the LVIN connection, to allow greater conduction through the device leads.
  • Clean the PCB following board assembly for best performance.
  • Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced into the device packaging during the cleaning process.
    • A low temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
  • Use conformal coating or potting, the deposition of an insulating polymer or other material layer over an assembled PCB, to reduce the pollution degree around the RES60A-Q1. This process reduces the requirements for creepage and clearance distances by eliminating or reducing the influence of pollutants.
  • Use groove cutting to attain a lower PCB creepage distance. For grooves wider than 1mm, the effective creepage distance is the existing creepage distance plus the width of the groove and twice the depth of the groove. This sum must equal or exceed the required creepage distance. The groove must not weaken the substrate to the point of failure to meet mechanical test requirements. All layers under the groove must be free from traces, vias, and pads to maintain the maximum creepage distance.