SGUS033A February   2002  – May 2016 SMJ320C6203

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description (continued)
  5. 5 Characteristics of the C6203 DSP
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics
    5. 7.5  Timing Requirements for CLKIN (PLL Used)
    6. 7.6  Timing Requirements for CLKIN [PLL Bypassed (x1)]
    7. 7.7  Timing Requirements for XCLKIN
    8. 7.8  Timing Requirements for Asynchronous Memory Cycles
    9. 7.9  Timing Requirements for Synchronous-Burst SRAM Cycles
    10. 7.10 Timing Requirements for Synchronous DRAM Cycles
    11. 7.11 Timing Requirements for the HOLD/HOLDA Cycles
    12. 7.12 Timing Requirements for Reset
    13. 7.13 Timing Requirements for Interrupt Response Cycles
    14. 7.14 Timing Requirements for Synchronous FIFO Interface
    15. 7.15 Timing Requirements for Asynchronous Peripheral Cycles
    16. 7.16 Timing Requirements With External Device as Bus Master
    17. 7.17 Timing Requirements With C62x as Bus Master
    18. 7.18 Timing Requirements With External Device as Asynchronous Bus Master
    19. 7.19 Timing Requirements for Expansion Bus Arbitration (Internal Arbiter Enabled)
    20. 7.20 Timing Requirements for McBSP
    21. 7.21 Timing Requirements for FSR when GSYNC = 1
    22. 7.22 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
    23. 7.23 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
    24. 7.24 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
    25. 7.25 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
    26. 7.26 Timing Requirements for Timer Inputs
    27. 7.27 Timing Requirements for JTAG Test Port
    28. 7.28 Switching Characteristics for CLKOUT2
    29. 7.29 Switching Characteristics for XFCLK
    30. 7.30 Asynchronous Memory Timing Switching Characteristics
    31. 7.31 Switching Characteristics for Synchronous-Burst SRAM Cycles
    32. 7.32 Switching Characteristics for Synchronous DRAM Cycles
    33. 7.33 Switching Characteristics for the HOLD/HOLDA Cycles
    34. 7.34 Switching Characteristics for Reset
    35. 7.35 Switching Characteristics for Interrupt Response Cycles
    36. 7.36 Switching Characteristics for Synchronous FIFO Interface
    37. 7.37 Switching Characteristics for Asynchronous Peripheral Cycles
    38. 7.38 Switching Characteristics With External Device as Bus Master
    39. 7.39 Switching Characteristics With C62x as Bus Master
    40. 7.40 Switching Characteristics With External Device as Asynchronous Bus Master
    41. 7.41 Switching Characteristics for Expansion Bus Arbitration (Internal Arbiter Enabled)
    42. 7.42 Switching Characteristics for Expansion Bus Arbitration (Internal Arbiter Disabled)
    43. 7.43 Switching Characteristics for McBSP
    44. 7.44 Switching Characteristics for McBSP as SPI Master or Slave
    45. 7.45 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
    46. 7.46 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
    47. 7.47 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
    48. 7.48 Switching Characteristics for DMAC Outputs
    49. 7.49 Switching Characteristics for Timer Outputs
    50. 7.50 Switching Characteristics for Power-Down Outputs
    51. 7.51 Switching Characteristics for JTAG Test Port
  8. 8 Parameter Measurement Information
    1. 8.1 Signal Transition Levels
    2. 8.2 Timing Parameters and Board Routing Analysis
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 Signal Groups Description
      2. 9.2.2 CPU (DSP Core) Description
      3. 9.2.3 Clock PLL
    3. 9.3 Register Maps
      1. 9.3.1 Memory Map Summary
      2. 9.3.2 Peripheral Register Descriptions
      3. 9.3.3 Interrupt Sources and Interrupt Selector
  10. 10Application and Implementation
    1. 10.1 Typical Application
      1. 10.1.1 Detailed Design Procedure
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 System-Level Design Considerations
    3. 11.3 Power-Supply Design Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Software Development Tools
        2. 12.1.2.2 Hardware Development Tools
      3. 12.1.3 Device and Development-Support Tool Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • GLP|429
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage CVDD(2) –0.3 1.8 V
DVDD(2) –0.3 4
Input voltage –0.3 4 V
Output voltage –0.3 4 V
TC Operating case temperature –55 125 °C
Temperature cycle (1000-cycle performance) –55 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.

7.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
CVDD Supply voltage, core 1.43 1.5 1.57 V
DVDD Supply voltage, I/O 3.14 3.3 3.46 V
VSS Supply ground 0 0 0 V
VIH High-level input voltage(1) 2 V
VIL Low-level input voltage(2) 0.8 V
IOH High-level output current −8 mA
IOL Low-level output current 8 mA
TC Operating case temperature −55 125 °C
(1) VIH is not production tested for: CLKMODE [2:0], CLKIN, XCLKIN, XCS.
(2) VIL is not production tested for: CLKIN, TRST.

7.3 Thermal Information

THERMAL METRIC(1) SMJ320C6203 UNIT
GLP (CFCBGA)
529 PINS
RθJA Junction-to-ambient thermal resistance 14.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance, measured to top of the package lid 7.3 °C/W
RθJB Junction-to-board thermal resistance, measured by soldering a thermocouple to one of the middle traces on the board at the edge of the package 6.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance, measured to bottom of solder ball 3.0 °C/W
RθJMA Junction-to-moving air thermal resistance 150 fpm 11.8 °C/W
250 fpm 11.1
500 fpm 10.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.4 Electrical Characteristics

over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage(1) DVDD = MIN, IOH = MAX 2.4 V
VOL Low-level output voltage(1) DVDD = MIN, IOL = MAX 0.6 V
II Input current(2) VI = VSS to DVDD ±10 µA
IOZ Off-state output current(3) VO = DVDD or 0 V ±10 µA
IDD2V Supply current, CPU + CPU memory access(4) CVDD = NOM, CPU clock = 200 MHz 340 mA
IDD2V Supply current, peripherals(4) CVDD = NOM, CPU clock = 200 MHz 235 mA
IDD3V Supply current, I/O pins(4) CVDD = NOM, CPU clock = 200 MHz 45 mA
Ci Input capacitance 12 pF
Co Output capacitance 15 pF
(1) VOH and VOL are not production tested for: CLKOUT1, EMU0, and EMU1.
(2) TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown.
(3) TDO is not production tested.
(4) Measured with average activity (50% high power/ 50% low power). For more details on CPU, peripheral, and I/O activity, see the TMS320C6000 Power Consumption Summary application report (SPRA486).

7.5 Timing Requirements for CLKIN (PLL Used)

see Figure 5(2)(3)(4)
NO. MIN MAX UNIT
1 tc(CLKIN) Cycle time, CLKIN 5 × M ns
2 tw(CLKINH) Pulse duration, CLKIN high (1)0.45C ns
3 tw(CLKINL) Pulse duration, CLKIN low (1)0.45C ns
4 tt(CLKIN) Transition time, CLKIN (1)0.5 ns
(1) This parameter is not production tested.
(2) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(3) M = The PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11).
(4) C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.

7.6 Timing Requirements for CLKIN [PLL Bypassed (x1)]

see Figure 5(2)(3)
NO. MIN MAX UNIT
1 tc(CLKIN) Cycle time, CLKIN 5 ns
2 tw(CLKINH) Pulse duration, CLKIN high (1)0.45C ns
3 tw(CLKINL) Pulse duration, CLKIN low (1)0.45C ns
4 tt(CLKIN) Transition time, CLKIN (1)0.6 ns
(1) This parameter is not production tested.
(2) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(3) C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. The maximum CLKIN cycle time in PLL bypass mode (x1) is 200 MHz.

7.7 Timing Requirements for XCLKIN

see Figure 6 (2)
NO. MIN MAX UNIT
1 tc(XCLKIN) Cycle time, XCLKIN 4P ns
2 tw(XCLKINH) Pulse duration, XCLKIN high (1)1.8P ns
3 tw(XCLKINL) Pulse duration, XCLKIN low (1)1.8P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns.

7.8 Timing Requirements for Asynchronous Memory Cycles

see Figure 9 through Figure 12 (2)(3)(4)(5)
NO. MIN MAX UNIT
3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 1 ns
4 th(AREH-EDV) Hold time, EDx valid after ARE high 4.9 ns
6 tsu(ARDYH-AREL) Setup time, ARDY high before ARE low −[(RST − 3) × P − 6] ns
7 th(AREL-ARDYH) Hold time, ARDY high after ARE low (RST − 3) × P + 2 ns
9 tsu(ARDYL-AREL) Setup time, ARDY low before ARE low −[(RST − 3) × P − 6] ns
10 th(AREL-ARDYL) Hold time, ARDY low after ARE low (RST − 3) × P + 2 ns
11 tw(ARDYH) Pulse duration, ARDY high (1)2P ns
15 tsu(ARDYH-AWEL) Setup time, ARDY high before AWE low −[(WST − 3) × P − 6] ns
16 th(AWEL-ARDYH) Hold time, ARDY high after AWE low (WST − 3) × P + 2 ns
18 tsu(ARDYL-AWEL) Setup time, ARDY low before AWE low −[(WST − 3) × P − 6] ns
19 th(AWEL-ARDYL) Hold time, ARDY low after AWE low (WST − 3) × P + 2 ns
(1) This parameter is not production tested.
(2) To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
(3) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed by the EMIF CE space control registers.
(4) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(5) The sum of RS and RST (or WS and WST) must be a minimum of 4 to use ARDY input to extend strobe width.

7.9 Timing Requirements for Synchronous-Burst SRAM Cycles

see Figure 13
NO. MIN MAX UNIT
7 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high 2.9 ns
8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high 2.3 ns

7.10 Timing Requirements for Synchronous DRAM Cycles

see Figure 15
NO. MIN MAX UNIT
7 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high 1.3 ns
8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high 2.9 ns

7.11 Timing Requirements for the HOLD/HOLDA Cycles

see Figure 21 (2)
NO. MIN MAX UNIT
3 toh(HOLDAL-HOLDL) Output hold time, HOLD low after HOLDA low (1)P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns

7.12 Timing Requirements for Reset

see Figure 22 (2)
NO. MIN MAX UNIT
1 tw(RST) Duration of the RESET pulse (PLL stable)(3) (1)10P ns
Duration of the RESET pulse (PLL needs to sync up)(4) (1)250 µs
10 tsu(XD) Setup time, XD configuration bits valid before RESET high(5) (1)5P ns
11 th(XD) Hold time, XD configuration bits valid after RESET high(5) (1)5P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 when CLKIN and PLL are stable.
(4) This parameter applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 only. (It does not apply to CLKMODE x1.) The RESET signal is not connected internally to the clock PLL circuit. However, the PLL may need up to 250 µs to stabilize following device power-up or after the PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See Clock PLL for PLL lock times.
(5) XD[31:0] are the boot configuration pins during device reset.

7.13 Timing Requirements for Interrupt Response Cycles

see Figure 23(2)
NO. MIN MAX UNIT
2 tw(ILOW) Duration of the interrupt pulse low (1)2P ns
3 tw(IHIGH) Duration of the interrupt pulse high (1)2P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

7.14 Timing Requirements for Synchronous FIFO Interface

see Figure 24 through Figure 26
NO. MIN MAX UNIT
5 tsu(XDV-XFCKH) Setup time, read XDx valid before XFCLK high 3 ns
6 th(XFCKH-XDV) Hold time, read XDx valid after XFCLK high 2.5 ns

7.15 Timing Requirements for Asynchronous Peripheral Cycles

see Figure 27 through Figure 30(2)(3)(4)(5)
NO. MIN MAX UNIT
3 tsu(XDV-XREH) Setup time, XDx valid before XRE high 4.5 ns
4 th(XREH-XDV) Hold time, XDx valid after XRE high 2.5 ns
6 tsu(XRDYH-XREL) Setup time, XRDY high before XRE low −[(RST − 3) × P − 6] ns
7 th(XREL-XRDYH) Hold time, XRDY high after XRE low (RST − 3) × P + 2 ns
9 tsu(XRDYL-XREL) Setup time, XRDY low before XRE low −[(RST − 3) × P − 6] ns
10 th(XREL-XRDYL) Hold time, XRDY low after XRE low (RST − 3) × P + 2 ns
11 tw(XRDYH) Pulse duration, XRDY high (1)2P ns
15 tsu(XRDYH-XWEL) Setup time, XRDY high before XWE low −[(WST − 3) × P − 6] ns
16 th(XWEL-XRDYH) Hold time, XRDY high after XWE low (WST − 3) × P + 2 ns
18 tsu(XRDYL-XWEL) Setup time, XRDY low before XWE low −[(WST − 3) × P − 6] ns
19 th(XWEL-XRDYL) Hold time, XRDY low after XWE low (WST − 3) × P + 2 ns
(1) This parameter is not production tested.
(2) To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input.
(3) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed by the expansion bus XCE space control registers.
(4) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(5) The sum of RS and RST (or WS and WST) must be a minimum of 4 to use XRDY input to extend strobe width.

7.16 Timing Requirements With External Device as Bus Master

see Figure 31 and Figure 32
NO. MIN MAX UNIT
1 tsu(XCSV-XCKIH) Setup time, XCS valid before XCLKIN high 3.5 ns
2 th(XCKIH-XCS) Hold time, XCS valid after XCLKIN high 2.8 ns
3 tsu(XAS-XCKIH) Setup time, XAS valid before XCLKIN high 3.5 ns
4 th(XCKIH-XAS) Hold time, XAS valid after XCLKIN high 2.8 ns
5 tsu(XCTL-XCKIH) Setup time, XCNTL valid before XCLKIN high 3.5 ns
6 th(XCKIH-XCTL) Hold time, XCNTL valid after XCLKIN high 2.8 ns
7 tsu(XWR-XCKIH) Setup time, XW/R valid before XCLKIN high(1) 3.5 ns
8 th(XCKIH-XWR) Hold time, XW/R valid after XCLKIN high(1) 2.8 ns
9 tsu(XBLTV-XCKIH) Setup time, XBLAST valid before XCLKIN high(2) 3.5 ns
10 th(XCKIH-XBLTV) Hold time, XBLAST valid after XCLKIN high(2) 2.8 ns
16 tsu(XBEV-XCKIH) Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high(3) 3.5 ns
17 th(XCKIH-XBEV) Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high(3) 2.8 ns
18 tsu(XD-XCKIH) Setup time, XDx valid before XCLKIN high 3.5 ns
19 th(XCKIH-XD) Hold time, XDx valid after XCLKIN high 2.8 ns
(1) XW/R input/output polarity selected at boot
(2) XBLAST input polarity selected at boot
(3) XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.

7.17 Timing Requirements With C62x as Bus Master

see Figure 33 through Figure 35
NO. MIN MAX UNIT
9 tsu(XDV-XCKIH) Setup time, XDx valid before XCLKIN high 3.5 ns
10 th(XCKIH-XDV) Hold time, XDx valid after XCLKIN high 2.8 ns
11 tsu(XRY-XCKIH) Setup time, XRDY valid before XCLKIN high(1) 3.5 ns
12 th(XCKIH-XRY) Hold time, XRDY valid after XCLKIN high(1) 2.8 ns
14 tsu(XBFF-XCKIH) Setup time, XBOFF valid before XCLKIN high 3.5 ns
15 th(XCKIH-XBFF) Hold time, XBOFF valid after XCLKIN high 2.8 ns
(1) XRDY operates as active-low ready input/output during host-port accesses.

7.18 Timing Requirements With External Device as Asynchronous Bus Master

see Figure 36 and Figure 37 (3)
NO. MIN MAX UNIT
1 tw(XCSL) Pulse duration, XCS low 4P ns
2 tw(XCSH) Pulse duration, XCS high 4P ns
3 tsu(XSEL-XCSL) Setup time, expansion bus select signals(2) valid before XCS low 1 ns
4 th(XCSL-XSEL) Hold time, expansion bus select signals(2) valid after XCS low 3.4 ns
10 th(XRYL-XCSL) Hold time, XCS low after XRDY low (1)P + 1.5 ns
11 tsu(XBEV-XCSH) Setup time, XBE[3:0]/XA[5:2] valid before XCS high(4) 1 ns
12 th(XCSH-XBEV) Hold time, XBE[3:0]/XA[5:2] valid after XCS high(4) 3 ns
13 tsu(XDV-XCSH) Setup time, XDx valid before XCS high 1 ns
14 th(XCSH-XDV) Hold time, XDx valid after XCS high 3 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) Expansion bus select signals include XCNTL and XR/W.
(4) XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.

7.19 Timing Requirements for Expansion Bus Arbitration (Internal Arbiter Enabled)

see Figure 38(2)
NO. MIN MAX UNIT
3 toh(XHDAH-XHDH) Output hold time, XHOLD high after XHOLDA high (1)P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

7.20 Timing Requirements for McBSP

see Figure 40(2)(3)
NO. MIN MAX UNIT
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P(4) ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext (1)P − 1(5) ns
CLKR int 9
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 2 ns
CLKR int 6
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 4 ns
CLKR int 8
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 0.5 ns
CLKR int 3
8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 5 ns
CLKX int 9
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 2 ns
CLKX int 6
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 4 ns
(1) This parameter is not production tested.
(2) CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
(3) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(4) The maximum bit rate for the C6203 device is 100 Mbps or CPU / 2 (the slower of the two). Take care to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR / X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz (P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
(5) The minimum CLKR/X pulse duration is either (P − 1) or 4 ns, whichever is larger. For example, when running parts at 200 MHz (P = 5 ns), use 4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P − 1) = 9 ns as the minimum CLKR/X pulse duration.

7.21 Timing Requirements for FSR when GSYNC = 1

see Figure 41
NO. MIN MAX UNIT
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high (1)4 ns
2 th(CKSH-FRH) Hold time, FSR high after CLKS high (1)4 ns
(1) This parameter is not production tested.

7.22 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

see Figure 42(2)(3)
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low (1)12 (1)2 − 3P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low (1)4 (1)5 + 6P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

7.23 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

see Figure 43(2)(3)
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high (1)12 (1)2 − 3P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high (1)4 (1)5 + 6P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

7.24 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

see Figure 44(2)(3)
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high (1)12 (1)2 − 3P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high (1)4 (1)5 + 6P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

7.25 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

see Figure 45(2)(3)
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low (1)12 (1)2 − 3P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low (1)4 (1)5 + 6P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

7.26 Timing Requirements for Timer Inputs

see Figure 47(2)
NO. MIN MAX UNIT
1 tw(TINPH) Pulse duration, TINP high (1)2P ns
2 tw(TINPL) Pulse duration, TINP low (1)2P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns

7.27 Timing Requirements for JTAG Test Port

see Figure 49
NO. MIN MAX UNIT
1 tc(TCK) Cycle time, TCK (1)35 ns
3 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high (1)11 ns
4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high (1)9 ns
(1) This parameter is not production tested.

7.28 Switching Characteristics for CLKOUT2

over recommended operating conditions for CLKOUT2(2)(3) (see Figure 7)
NO. PARAMETER MIN MAX UNIT
1 tc(CKO2) Cycle time, CLKOUT2 (1)2P − 0.7 (1)2P + 0.7 ns
2 tw(CKO2H) Pulse duration, CLKOUT2 high (1)P − 0.7 (1)P + 0.7 ns
3 tw(CKO2L) Pulse duration, CLKOUT2 low (1)P − 0.7 (1)P + 0.7 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns.
(3) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

7.29 Switching Characteristics for XFCLK

over recommended operating conditions for XFCLK(2)(3) (see Figure 8)
NO. PARAMETER MIN MAX UNIT
1 tc(XFCK) Cycle time, XFCLK (1)D × P − 0.7 (1)D × P + 0.7 ns
2 tw(XFCKH) Pulse duration, XFCLK high (1)(D/2) × P − 0.7 (1)(D/2) × P + 0.7 ns
3 tw(XFCKL) Pulse duration, XFCLK low (1)(D/2) × P − 0.7 (1)(D/2) × P + 0.7 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns.
(3) D = 8, 6, 4, or 2; FIFO clock divide ratio, user-programmable

7.30 Asynchronous Memory Timing Switching Characteristics

over recommended operating conditions for asynchronous memory cycles(2)(3)(4)(5) (see Figure 9 through Figure 12)
NO. PARAMETER MIN TYP MAX UNIT
1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS × P − 2 ns
2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid (1)RH × P − 2 ns
5 tw(AREL) Pulse duration, ARE low RST × P ns
8 td(ARDYH-AREH) Delay time, ARDY high to ARE high (1)3P (1)4P + 5 ns
12 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS × P − 3 ns
13 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid (1)WH × P − 2 ns
14 tw(AWEL) Pulse duration, AWE low WST × P ns
17 td(ARDYH-AWEH) Delay time, ARDY high to AWE high (1)3P (1)4P + 5 ns
(1) This parameter is not production tested.
(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed by the EMIF CE space control registers.
(3) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(4) The sum of RS and RST (or WS and WST) must be a minimum of 4 to use ARDY input to extend strobe width.
(5) Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional 7P ns following the end of the cycle.

7.31 Switching Characteristics for Synchronous-Burst SRAM Cycles

over recommended operating conditions for synchronous-burst SRAM cycles(2)(3) (see Figure 13 and Figure 14)
NO. PARAMETER MIN MAX UNIT
1 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high P − 1.7 ns
2 toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high (1)P − 4 ns
3 tosu(BEV-CKO2H) Output setup time, BEx valid before CLKOUT2 high P − 1.7 ns
4 toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high (1)P − 4 ns
5 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high P − 1.7 ns
6 toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high (1)P − 4 ns
9 tosu(ADSV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2 high P − 1.7 ns
10 toh(CKO2H-ADSV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high (1)P − 4 ns
11 tosu(OEV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high P − 1.7 ns
12 toh(CKO2H-OEV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high (1)P − 4 ns
13 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 high(4) P − 2.3 ns
14 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high (1)P − 4 ns
15 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2 high P − 1.7 ns
16 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high (1)P − 4 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
(4) For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time.

7.32 Switching Characteristics for Synchronous DRAM Cycles

over recommended operating conditions for synchronous DRAM cycles for C6203B Rev. 2(2)(3) (see Figure 15 through Figure 20)
NO. PARAMETER MIN MAX UNIT
1 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high P − 0.9 ns
2 toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high (1)P − 4.1 ns
3 tosu(BEV-CKO2H) Output setup time, BEx valid before CLKOUT2 high P − 0.9 ns
4 toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high (1)P − 4.1 ns
5 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high P − 0.9 ns
6 toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high (1)P − 4.1 ns
9 tosu(CASV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2 high P − 0.9 ns
10 toh(CKO2H-CASV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high (1)P − 4.1 ns
11 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 high(4) P − 1.5 ns
12 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high (1)P − 4.1 ns
13 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2 high P − 0.9 ns
14 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high (1)P − 4.1 ns
15 tosu(SDA10V-CKO2H) Output setup time, SDA10 valid before CLKOUT2 high P − 0.9 ns
16 toh(CKO2H-SDA10IV) Output hold time, SDA10 invalid after CLKOUT2 high (1)P − 4.1 ns
17 tosu(RASV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high P − 0.9 ns
18 toh(CKO2H-RASV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high (1)P − 4.1 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
(4) For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time.

7.33 Switching Characteristics for the HOLD/HOLDA Cycles

over recommended operating conditions for the HOLD/HOLDA cycles(2)(3) (see Figure 21)
NO. PARAMETER MIN MAX UNIT
1 td(HOLDL-EMHZ) Delay time, HOLD low to EMIF bus high impedance (1)3P   (4) ns
2 td(EMHZ-HOLDAL) Delay time, EMIF bus high impedance to HOLDA low (1)0 (1)2P ns
4 td(HOLDH-EMLZ) Delay time, HOLD high to EMIF bus low impedance (1)3P (1)7P ns
5 td(EMLZ-HOLDAH) Delay time, EMIF bus low impedance to HOLDA high (1)0 (1)2P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) EMIF bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/ SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
(4) All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

7.34 Switching Characteristics for Reset

over recommended operating conditions during reset(2)(3) (see Figure 22)
NO. PARAMETER MIN MAX UNIT
2 td(RSTL-CKO2IV) Delay time, RESET low to CLKOUT2 invalid (1)P ns
3 td(RSTH-CKO2V) Delay time, RESET high to CLKOUT2 valid (1)4P ns
4 td(RSTL-HIGHIV) Delay time, RESET low to high group invalid (1)P ns
5 td(RSTH-HIGHV) Delay time, RESET high to high group valid (1)4P ns
6 td(RSTL-LOWIV) Delay time, RESET low to low group invalid (1)P ns
7 td(RSTH-LOWV) Delay time, RESET high to low group valid (1)4P ns
8 td(RSTL-ZHZ) Delay time, RESET low to Z group high impedance (1)P ns
9 td(RSTH-ZV) Delay time, RESET high to Z group valid (1)4P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) High group consists of: XFCLK, HOLDA
Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1, FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD, and XHOLDA

7.35 Switching Characteristics for Interrupt Response Cycles

over recommended operating conditions during interrupt response cycles(2)(3) (see Figure 23)
NO. PARAMETER MIN MAX UNIT
1 tR(EINTH − IACKH) Response time, EXT_INTx high to IACK high (1)9P ns
4 td(CKO2L-IACKV) Delay time, CLKOUT2 low to IACK valid (1)−1.5 (1)10 ns
5 td(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid (1)−2.0 (1)10 ns
6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid (1)−2.0 (1)10 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) When CLKOUT2 is in half mode (see CLKOUT2 in ), timings are based on falling edges.

7.36 Switching Characteristics for Synchronous FIFO Interface

over recommended operating conditions for synchronous FIFO interface (see Figure 24 through Figure 26)
NO. PARAMETER MIN MAX UNIT
1 td(XFCKH-XCEV) Delay time, XFCLK high to XCEx valid (1)−1.5 4.5 ns
2 td(XFCKH-XAV) Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid(2) (1)−1.5 4.5 ns
3 td(XFCKH-XOEV) Delay time, XFCLK high to XOE valid (1)−1.5 4.5 ns
4 td(XFCKH-XREV) Delay time, XFCLK high to XRE valid (1)−1.5 4.5 ns
7 td(XFCKH-XWEV) Delay time, XFCLK high to XWE/XWAIT(3) valid (1)−1.5 4.5 ns
8 td(XFCKH-XDV) Delay time, XFCLK high to XDx valid 4.5 ns
9 td(XFCKH-XDIV) Delay time, XFCLK high to XDx invalid (1)−1.5 ns
(1) This parameter is not production tested.
(2) XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
(3) XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.

7.37 Switching Characteristics for Asynchronous Peripheral Cycles

over recommended operating conditions for asynchronous peripheral cycles(2)(3)(4)(5) (see Figure 27 through Figure 30)
NO. PARAMETER MIN TYP MAX UNIT
1 tosu(SELV-XREL) Output setup time, select signals valid to XRE low RS × P − 2 ns
2 toh(XREH-SELIV) Output hold time, XRE low to select signals invalid (1)RH × P − 2 ns
5 tw(XREL) Pulse duration, XRE low RST × P ns
8 td(XRDYH-XREH) Delay time, XRDY high to XRE high (1)3P (1)4P + 5 ns
12 tosu(SELV-XWEL) Output setup time, select signals valid to XWE low WS × P − 3 ns
13 toh(XWEH-SELIV) Output hold time, XWE low to select signals invalid (1)WH × P − 2 ns
14 tw(XWEL) Pulse duration, XWE low WST x P ns
17 td(XRDYH-XWEH) Delay time, XRDY high to XWE high (1)3P (1)4P + 5 ns
(1) This parameter is not production tested.
(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed by the expansion bus XCE space control registers.
(3) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(4) The sum of RS and RST (or WS and WST) must be a minimum of 4 to use XRDY input to extend strobe width.
(5) Select signals include: XCEx, XBE[3:0]/XA[5:2], XOE; and for writes, include XD[31:0], with the exception that XCEx can stay active for an additional 7P ns following the end of the cycle.

7.38 Switching Characteristics With External Device as Bus Master

over recommended operating conditions with external device as bus master(2) (see Figure 31 and Figure 32)
NO. PARAMETER MIN MAX UNIT
11 td(XCKIH-XDLZ) Delay time, XCLKIN high to XDx low impedance (1)0 ns
12 td(XCKIH-XDV) Delay time, XCLKIN high to XDx valid 4P ns
13 td(XCKIH-XDIV) Delay time, XCLKIN high to XDx invalid (1)5 ns
14 td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx high impedance (1)4P ns
15 td(XCKIH-XRY) Delay time, XCLKIN high to XRDY invalid(3) (1)5 (1)4P ns
20 td(XCKIH-XRYLZ) Delay time, XCLKIN high to XRDY low impedance (1)5 (1)4P ns
21 td(XCKIH-XRYHZ) Delay time, XCLKIN high to XRDY high impedance(3) (1)2P + 5 (1)7P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) XRDY operates as active-low ready input/output during host-port accesses.

7.39 Switching Characteristics With C62x as Bus Master

over recommended operating conditions with C62x as bus master(2) (see Figure 33 through Figure 35)
NO. PARAMETER MIN MAX UNIT
1 td(XCKIH-XASV) Delay time, XCLKIN high to XAS valid (1)5 4P ns
2 td(XCKIH-XWRV) Delay time, XCLKIN high to XW/R valid(3) (1)5 4P ns
3 td(XCKIH-XBLTV) Delay time, XCLKIN high to XBLAST valid(4) (1)5 4P ns
4 td(XCKIH-XBEV) Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid(5) (1)5 4P ns
5 td(XCKIH-XDLZ) Delay time, XCLKIN high to XDx low impedance (1)0 ns
6 td(XCKIH-XDV) Delay time, XCLKIN high to XDx valid 4P ns
7 td(XCKIH-XDIV) Delay time, XCLKIN high to XDx invalid (1)5 ns
8 td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx high impedance (1)4P ns
13 td(XCKIH-XWTV) Delay time, XCLKIN high to XWE/XWAIT valid(6) (1)5 4P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) XW/R input/output polarity selected at boot.
(4) XBLAST output polarity is always active low.
(5) XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
(6) XWE/XWAIT operates as XWAIT output signal during host-port accesses.

7.40 Switching Characteristics With External Device as Asynchronous Bus Master

over recommended operating conditions with external device as asynchronous bus master(2) (see Figure 36 and Figure 37)
NO. PARAMETER MIN MAX UNIT
5 td(XCSL-XDLZ) Delay time, XCS low to XDx low impedance (1)0 ns
6 td(XCSH-XDIV) Delay time, XCS high to XDx invalid (1)0 (1)12 ns
7 td(XCSH-XDHZ) Delay time, XCS high to XDx high impedance (1)4P ns
8 td(XRYL-XDV) Delay time, XRDY low to XDx valid (1)−4 (1)1 ns
9 td(XCSH-XRYH) Delay time, XCS high to XRDY high (1)0 12 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

7.41 Switching Characteristics for Expansion Bus Arbitration (Internal Arbiter Enabled)

over recommended operating conditions for expansion bus arbitration (internal arbiter enabled)(2)(3) (see Figure 38)
NO. PARAMETER MIN MAX UNIT
1 td(XHDH-XBHZ) Delay time, XHOLD high to expansion bus high impedance (1)3P   (4) ns
2 td(XBHZ-XHDAH) Delay time, expansion bus high impedance to XHOLDA high (1)0 (1)2P ns
4 td(XHDL-XHDAL) Delay time, XHOLD low to XHOLDA low (1)3P ns
5 td(XHDAL-XBLZ) Delay time, XHOLDA low to expansion bus low impedance (1)0 (1)2P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) Expansion bus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
(4) All pending expansion bus transactions are allowed to complete before XHOLDA is asserted.

7.42 Switching Characteristics for Expansion Bus Arbitration (Internal Arbiter Disabled)

over recommended operating conditions for expansion bus arbitration (internal arbiter disabled)(2) (see Figure 39)
NO. PARAMETER MIN MAX UNIT
1 td(XHDAH-XBLZ) Delay time, XHOLDA high to expansion bus low impedance(3) (1)2P (1)2P + 10 ns
2 td(XBHZ-XHDL) Delay time, expansion bus high impedance to XHOLD low(3) (1)0 (1)2P ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) Expansion bus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.

7.43 Switching Characteristics for McBSP

over recommended operating conditions for McBSP(2)(3) (see Figure 40)
NO. PARAMETER MIN MAX UNIT
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input (1)4 (1)16 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int (1)2P(4)(5) ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int (1)C − 2(6) (1)C + 2(6) ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int (1)−3 (1)3 ns
CLKX int (1)−3 3
9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext (1)−3 9 ns
CLKX int (1)−1 (1)5
12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high CLKX ext (1)2 (1)9 ns
CLKX int (1)−1 (1)4
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext (1)2 (1)11 ns
14 td(FXH-DXV) Delay time, FSX high to DX valid only applies when in data delay 0 (XDATDLY = 00b) mode. FSX int (1)−1 (1)5 ns
FSX ext (1)0 (1)10
(1) This parameter is not production tested.
(2) CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
(3) Minimum delay times also represent minimum output hold times.
(4) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(5) The maximum bit rate for the C6203 device is 100 Mbps or CPU / 2 (the slower of the two). Take care to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR / X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz (P = 5 ns), use 10 ns as the minimum CLKR / X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR / X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1 / CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse duration = (CLKGDV/2 + 1) × S if CLKGDV is even
= (CLKGDV + 1) / 2 × S if CLKGDV is odd or zero
L = CLKX low pulse duration = (CLKGDV/2) × S if CLKGDV is even
= (CLKGDV + 1) / 2 × S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.

7.44 Switching Characteristics for McBSP as SPI Master or Slave

over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0(2)(3) (see Figure 42)
NO. PARAMETER MASTER(4) SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low(5) (1)T − 2 (1)T + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high(6) (1)L − 2 (1)L + 3 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid (1)−4 (1)4 (1)3P + 4 (1)5P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low (1)L − 2 (1)L + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high (1)P + 3 (1)3P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid (1)2P + 2 (1)4P + 17 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(4) S = sample rate generator input clock = P if CLKSM = 1 (P = 1 / CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) × S
H = CLKX high pulse duration = (CLKGDV / 2 + 1) × S if CLKGDV is even
= (CLKGDV + 1) / 2 × S if CLKGDV is odd or zero
L = CLKX low pulse duration = (CLKGDV / 2) × S if CLKGDV is even
= (CLKGDV + 1) / 2 × S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
(5) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(6) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

7.45 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0(2)(3) (see Figure 43)
NO. PARAMETER MASTER(4) SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low(5) (1)L − 2 (1)L + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high(6) (1)T − 2 (1)T + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid (1)−4 (1)4 (1)3P + 4 (1)5P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low (1)−2 (1)4 (1)3P + 3 (1)5P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid (1)H − 2 (1)H + 4 (1)2P + 2 (1)4P + 17 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(4) S = Sample rate generator input clock = P if CLKSM = 1 (P = 1 / CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) × S
H = CLKX high pulse duration = (CLKGDV / 2 + 1) × S if CLKGDV is even
= (CLKGDV + 1) / 2 × S if CLKGDV is odd or zero
L = CLKX low pulse duration = (CLKGDV / 2) × S if CLKGDV is even
= (CLKGDV + 1) / 2 × S if CLKGDV is odd or zero
The maximum transfer rate for SPI mode is limited to the above AC timing constraints.
(5) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(6) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

7.46 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1(2)(3) (see Figure 44)
NO. PARAMETER MASTER(4) SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high(5) (1)T − 2 (1)T + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low(6) (1)H − 2 (1)H + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid (1)−4 (1)4 (1)3P + 4 (1)5P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high (1)H − 2 (1)H + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high (1)P + 3 (1)3P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid (1)2P + 2 (1)4P + 17 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(4) S = Sample rate generator input clock = P if CLKSM = 1 (P = 1 / CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) × S
H = CLKX high pulse duration = (CLKGDV / 2 + 1) × S if CLKGDV is even = (CLKGDV + 1) / 2 × S if CLKGDV is odd or zero
L = CLKX low pulse duration = (CLKGDV / 2) × S if CLKGDV is even = (CLKGDV + 1) / 2 × S if CLKGDV is odd or zero
The maximum transfer rate for SPI mode is limited to the above AC timing constraints.
(5) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(6) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

7.47 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1(2)(3) (see Figure 45)
NO. PARAMETER MASTER(4) SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high(5) (1)H − 2 (1)H + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low(6) (1)T − 2 (1)T + 2 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid (1)−4 (1)4 (1)3P + 4 (1)5P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX height (1)−2 (1)4 (1)3P + 3 (1)5P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid (1)L − 2 (1)L + 5 (1)2P + 2 (1)4P + 17 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
(3) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(4) S = Sample rate generator input clock = P if CLKSM = 1 (P = 1 / CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) × S
H = CLKX high pulse duration = (CLKGDV / 2 + 1) × S if CLKGDV is even
= (CLKGDV + 1) / 2 × S if CLKGDV is odd or zero
L = CLKX low pulse duration = (CLKGDV / 2) × S if CLKGDV is even
= (CLKGDV + 1) / 2 × S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
(5) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(6) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

7.48 Switching Characteristics for DMAC Outputs

over recommended operating conditions for DMAC outputs(2) (see Figure 46)
NO. PARAMETER MIN MAX UNIT
1 tw(DMACH) Pulse duration, DMAC high (1)2P − 3 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

7.49 Switching Characteristics for Timer Outputs

over recommended operating conditions for timer outputs(2) (see Figure 47)
NO. PARAMETER MIN MAX UNIT
3 tw(TOUTH) Pulse duration, TOUT high (1)2P − 3 ns
4 tw(TOUTL) Pulse duration, TOUT low (1)2P − 3 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

7.50 Switching Characteristics for Power-Down Outputs

over recommended operating conditions for power-down outputs(2) (see Figure 48)
NO. PARAMETER MIN MAX UNIT
1 tw(PDH) Pulse duration, PD high (1)2P−3 ns
(1) This parameter is not production tested.
(2) P = 1 / CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

7.51 Switching Characteristics for JTAG Test Port

over recommended operating conditions for JTAG test port (see Figure 49)
NO. PARAMETER MIN MAX UNIT
2 td(TCKL-TDOV) Delay time, TCK low to TDO valid (1)−4.5 (1)13.5 ns
(1) This parameter is not production tested.