SCLS100F December   1982  – April 2021 SN54HC86 , SN74HC86

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics - 74
    5. 6.5 Electrical Characteristics - 54
    6. 6.6 Switching Characteristics - 74
    7. 6.7 Switching Characteristics - 54
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • J|14
  • FK|20
  • W|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

This device contains four independent 2-input XOR gates. Each gate performs the Boolean function Y = A ⊕ B in positive logic.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74HC86D SOIC (14) 8.70 mm × 3.90 mm
SN74HC86N PDIP (14) 19.30 mm × 6.40 mm
SN74HC86NS SO (14) 10.20 mm × 5.30 mm
SN74HC86PW TSSOP (14) 5.00 mm × 4.40 mm
SN54HC86J CDIP (14) 21.30 mm × 7.60 mm
SN54HC86W CFP (14) 9.20 mm × 6.29 mm
SN54HC86FK LCCC (20) 8.90 mm × 8.90 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-7EADAFD1-6E37-4780-86D5-691F5787BE4D-low.gifFunctional pinout