SLLSFC4 July   2019 SN65C1168E-SEP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Driver Section Electrical Characteristics
    6. 6.6 Receiver Section Electrical Characteristics
    7. 6.7 Driver Section Switching Characteristics
    8. 6.8 Receiver Section Switching Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Active High Driver Output Enables
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Receiver Section Electrical Characteristics

over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIT+ Positive-going input threshold voltage,
differential input		 0.2 V
VIT– Negative-going input threshold voltage,
differential input		 –0.2(2) V
Vhys Input hysteresis (VIT+  – VIT–) 60 mV
VOH High-level output voltage VID = 200 mV, IOH = –6 mA 3.8 4.2 V
VOL Low-level output voltage VID = –200 mV, IOL = 6 mA 0.1 0.3 V
II Line input current Other input at 0 V VI = 10 V 1.5 mA
VI = –10 V –2.5
rI Input resistance VIC = –7 V to 7 V, other input at 0 V 4 17 kΩ
ICC Supply current (total package) No load,
Enabled		 VI = VCC or GND 4 6 mA
VIH = 2.4 V or 0.5 V(3) 5 9
ICC Supply current (total package)(4) No load VI = VCC or GND 17 mA
VI = 2.4 or 0.5 V(4) 16
(1) All typical values are at VCC = 5 V and TA = 25°C.
(2) The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode input voltage and threshold voltage levels only.
(3) Refer to TIA/EIA-422-B for exact conditions.
(4) 25°C only. Post 20-krad(Si) HDR TID using worst case static biasing.