SLLSES6C February   2016  – December 2021 SN65DP141

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Switching Characteristics, I2C Interface
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DC and AC Independent Gain Control
      2. 8.3.2 Two-Wire Serial Interface and Control Logic
      3. 8.3.3 Bus Idle
      4. 8.3.4 Start Data Transfer
      5. 8.3.5 Stop Data Transfer
      6. 8.3.6 Data Transfer
      7. 8.3.7 Acknowledge
    4. 8.4 Device Functional Modes
      1. 8.4.1 TRACE and CABLE Equalization Modes
      2. 8.4.2 Control Modes
      3. 8.4.3 GPIO MODE
      4. 8.4.4 I2C Mode
    5. 8.5 Register Maps
      1. 8.5.1  Register 0x00 (General Device Settings) (offset = 00000000) [reset = 00000000]
      2. 8.5.2  Register 0x01 (Channel Enable) (offset = 00000000) [reset = 00000000]
      3. 8.5.3  Register 0x02 (Channel 0 Control Settings) (offset = 00000000) [reset = 00000000]
      4. 8.5.4  Register 0x03 (Channel 0 Enable Settings) (offset = 00000000) [reset = 00000000]
      5. 8.5.5  Register 0x05 (Channel 1 Control Settings) (offset = 00000000) [reset = 00000000]
      6. 8.5.6  Register 0x06 (Channel 1 Enable Settings) (offset = 00000000) [reset = 00000000]
      7. 8.5.7  Register 0x08 (Channel 2 Control Settings) (offset = 00000000) [reset = 00000000]
      8. 8.5.8  Register 0x09 (Channel 2 Enable Settings) (offset = 00000000) [reset = 00000000]
      9. 8.5.9  Register 0x0B (Channel 3 Control Settings) (offset = 00000000) [reset = 00000000]
      10. 8.5.10 Register 0x0C (Channel 3 Control Settings) (offset = 00000000) [reset = 00000000]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
CML OUTPUTS (OUT[3:0]_P, OUT[3:0]_N)
tRRise time (1)Input signal with 30 ps rise time, 20% to 80%,
See Figure 7-3		31ps
tFFall time (1)Input signal with 30 ps fall time, 20% to 80%,
See Figure 7-3		32ps
SDD22Differential output return loss6 GHz (12 Gbps)-14dB
4.05 GHz (HBR3, 8.1 Gbps)–9.33dB
4.05 GHz (HBR3, 8.1 Gbps)–6.35dB
1.35 GHz (HBR, 2.7Gbps)–3.5dB
tPLHLow-to-high propagation delaySee Figure 7-265ps
tPHLHigh-to-low propagation delay65ps
tSK(O)Inter-Pair (lane to lane) output skew (2)All outputs terminated with 100 Ω,
See Figure 7-4		8ps
tSK(PP)Part-to-part skew (3)All outputs terminated with 100 Ω50ps
rOTSingle ended output resistanceSingle ended on-chip termination to VCC,
Outputs are AC coupled		50Ω
rOMOutput termination mismatch at 1 MHz GUID-0D839D5A-D3A2-4806-ACFC-A94CB4CE7923-low.gif5%
Channel-to-channel isolationFrequency at 6 GHz3545dB
Output referred noise(4)10 MHz to 6 GHz, No other noise source present, VOD = LOW400µVRMS
10 MHz to 6 GHz, No other noise source present, VOD = HIGH500µVRMS
EQUALIZATION
GAt 6 GHz input signalEqualization Gain, EQ = MAX15dB
V(pre)Output pre-cursor pre-emphasisInput signal with 3.75 pre-cursor and measure it on the output signal,
See Figure 7-5		3.75dB
V(pst)Output post-cursor pre-emphasisInput signal with 12 dB post-cursor and measure it on the output signal,
See Figure 7-5		12dB
(1) Rise and Fall measurements include board and channel effects of the test environment, refer to Figure 7-1 and Figure 7-3.
(2) tSK(O) is the magnitude of the time difference between the channels.
(3) tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same
(4) All noise sources added.