SLLSE49E September   2010  – October 2024 SN65HVD1780-Q1 , SN65HVD1781-Q1 , SN65HVD1782-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings—AEC
    3. 5.3  ESD Ratings—IEC
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Power Dissipation Ratings
    8. 5.8  Switching Characteristics
    9. 5.9  Package Dissipation Ratings
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bus Fault Conditions
      2. 7.3.2 Receiver Failsafe
      3. 7.3.3 Hot-Plugging
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Bus Loading
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stub Length
        2. 8.2.2.2 Receiver Failsafe
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOD| Driver differential output voltage magnitude RL = 60 Ω, 4.75 V ≤ VCC 375 Ω
on each output to –7 V to 12 V, SeeFigure 6-1		 TA < 85°C 1.5 V
TA < 125°C 1.4
RL = 54 Ω,
4.75 V ≤ VCC ≤ 5.25 V		 TA < 85°C 1.7 2
TA < 125°C 1.5
RL = 54 Ω,
3.15 V ≤ VCC ≤ 3.45 V		 0.8 1
RL = 100 Ω,
4.75 V ≤ VCC ≤ 5.25 V		 TA < 85°C 2.2 2.5
TA < 125°C 2
Δ|VOD| Change in magnitude of driver differential output voltage RL = 54 Ω –50 0 50 mV
VOC(SS) Steady-state common-mode output voltage 1 VCC/2 3 V
ΔVOC Change in differential driver output common-mode voltage –50 0 50 mV
VOC(PP) Peak-to-peak driver common-mode output voltage Center of two 27-Ω load resistors,
See Figure 6-2		 500 mV
COD Differential output capacitance 23 pF
VIT+ Positive-going receiver differential input voltage threshold –100 –35 mV
VIT– Negative-going receiver differential input voltage threshold –180 –150 mV
VHYS Receiver differential input voltage threshold hysteresis
(VIT+ – VIT–)(1)		 30 50 mV
VOH Receiver high-level output voltage IOH = –8 mA 2.4 VCC – 0.3 V
VOL Receiver low-level output voltage IOL = 8 mA TA < 85°C 0.2 0.4 V
TA < 125°C 0.5
II(LOGIC) Driver input, driver enable, and receiver enable input current –50 50 μA
IOZ Receiver output high-impedance current VO = 0 V or VCC, RE at VCC –1 1 μA
IOS Driver short-circuit output current –200 200 mA
II(BUS) Bus input current (disabled driver) VCC = 3.15 to 5.5 V or
VCC = 0 V, DE at 0 V		 VI = 12 V HVD1780-Q1, HVD1781-Q1 75 100 μA
HVD1782-Q1 400 500
VI = –7 V HVD1780-Q1, HVD1781-Q1 –60 –40
HVD1782-Q1 -400 -300
ICC Supply current (quiescent) Driver and receiver enabled DE = VCC, RE = GND,
no load		 4 6 mA
Driver enabled, receiver disabled DE = VCC, RE = VCC,
no load		 3 5
Driver disabled, receiver enabled DE = GND, RE = GND,
no load		 2 4
Driver and receiver disabled, standby mode DE = GND, D = open,
RE = VCC, no load, TA < 85°C		 0.15 1 μA
DE = GND, D = open,
RE = VCC, no load, TA < 125°C		 12
Supply current (dynamic) See the Typical Characteristics section
(1) Specified by design. Not production tested.