SLLSFG7B September   2020  – November 2022 SN65MLVD203B

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics – Driver
    7. 6.7  Electrical Characteristics – Receiver
    8. 6.8  Switching Characteristics – Driver
    9. 6.9  Switching Characteristics – Receiver
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Power-On-Reset
      2. 8.3.2 ESD Protection
      3. 8.3.3 RX Maximum Jitter While DE Toggling
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with VCC < 1.5 V
      2. 8.4.2 Operations with 1.5 V ≤ VCC < 3 V
      3. 8.4.3 Operation with 3 V ≤ VCC < 3.6 V
      4. 8.4.4 Device Function Tables
      5. 8.4.5 Equivalent Input and Output Schematic Diagrams
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multipoint Communications
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1  Supply Voltage
        2. 9.2.3.2  Supply Bypass Capacitance
        3. 9.2.3.3  Driver Input Voltage
        4. 9.2.3.4  Driver Output Voltage
        5. 9.2.3.5  Termination Resistors
        6. 9.2.3.6  Receiver Input Signal
        7. 9.2.3.7  Receiver Input Threshold (Failsafe)
        8. 9.2.3.8  Receiver Output Signal
        9. 9.2.3.9  Interconnecting Media
        10. 9.2.3.10 PCB Transmission Lines
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Microstrip vs. Stripline Topologies
        2. 9.4.1.2 Dielectric Type and Board Construction
        3. 9.4.1.3 Recommended Stack Layout
        4. 9.4.1.4 Separation Between Traces
        5. 9.4.1.5 Crosstalk and Ground Bounce Minimization
        6. 9.4.1.6 Decoupling
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics – Driver

over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX UNIT

|VYZ| 		Differential output voltage magnitude (4) See Figure 7-2 480 650 mV

Δ|VYZ| 		Change in differential output voltage magnitude between logic states –50 50 mV
VOS(SS) Steady-state common-mode output voltage See Figure 7-3 0.8 1.2 V
ΔVOS(SS) Change in steady-state common-mode output voltage between logic states –50 50 mV
VOS(PP) Peak-to-peak common-mode output voltage 150 mV
VY(OC)
Maximum steady-state open-circuit output voltage See Figure 7-7 0 2.4 V
VZ(OC)
Maximum steady-state open-circuit output voltage 0 2.4 V
VP(H) Voltage overshoot, low-to-high level output See Figure 7-5 1.2 VSS V
VP(L) Voltage overshoot, high-to-low level output –0.2 VSS V
IIH High-level input current (D, DE) VIH = 2 V to VCC 0 10 µA
IIL Low-level input current (D, DE)   VIL = GND to 0.8 V -1 10 µA
|IOS| Differential short-circuit output current magnitude   See Figure 7-4 24 mA
IOZ High-impedance state output current (driver only) –1.4 V ≤ (VY or VZ) ≤ 3.8 V,
Other output = 1.2 V		 –15 10 µA
IO(OFF) Power-off output current –1.4 V ≤ (VY or VZ) ≤ 3.8 V, Other output = 1.2 V, 0 V ≤ VCC≤ 1.5 V –10 10 µA
CY or CZ Output capacitance VI = 0.4 sin(30E6πt) + 0.5 V,(3)
Other input at 1.2 V, driver disabled		 6 pF
CYZ Differential output capacitance VAB = 0.4 sin(30E6πt) V, (3)
Driver disabled		 4.5 pF
CY/Z Output capacitance balance, (CY/CZ) 0.98 1.02
(1) The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25°C and with a 3.3-V supply voltage.
(3) HP4194A impedance analyzer (or equivalent)
(4) Measurement equipment accuracy is 10 mV at –40°C