SLLS573E December   2003  – March 2024 SN65MLVD200A , SN65MLVD202A , SN65MLVD204A , SN65MLVD205A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics – Driver
    7. 6.7  Electrical Characteristics – Receiver
    8. 6.8  Electrical Characteristics – BUS Input and Output
    9. 6.9  Switching Characteristics – Driver
    10. 6.10 Switching Characteristics – Receiver
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-On Reset
      2. 8.3.2 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Function Tables
      2. 8.4.2 Equivalent Input and Output Schematic Diagrams
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Supply Voltage
        2. 9.2.2.2  Supply Bypass Capacitance
        3. 9.2.2.3  Driver Input Voltage
        4. 9.2.2.4  Driver Output Voltage
        5. 9.2.2.5  Termination Resistors
        6. 9.2.2.6  Receiver Input Signal
        7. 9.2.2.7  Receiver Input Threshold (Failsafe)
        8. 9.2.2.8  Receiver Output Signal
        9. 9.2.2.9  Interconnecting Media
        10. 9.2.2.10 PCB Transmission Lines
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip Versus Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.10 Switching Characteristics – Receiver

over recommended operating conditions unless otherwise noted
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
tPLHPropagation delay time, low-to-high-level outputCL = 15 pF, See Figure 7-1023.66ns
tPHLPropagation delay time, high-to-low-level output23.66ns
trOutput signal rise time12.3ns
tfOutput signal fall time12.3ns
tsk(p)Pulse skew (|tpHL – tpLH|)Type 1100300ps
Type 2300500ps
tsk(pp)Part-to-part skew(2)1ns
tjit(per)Period jitter, rms (1 standard deviation)(3)50-MHz clock input(4)47ps
tjit(pp)Peak-to-peak jitter(3) (6)Type 1100 Mbps 215 –1 PRBS input(5)200700ps
Type 2225800ps
tPHZDisable time, high-level-to-high-impedance outputSee Figure 7-11610ns
tPLZDisable time, low-level-to-high-impedance output610ns
tPZHEnable time, high-impedance-to-high-level output1015ns
tPZLEnable time, high-impedance-to-low-level output1015ns
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) Part-to-part skew is defined as the difference in propagation delays between two devices that operate at the same V/T conditions.
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) VID = 200 mVpp (MLVD200A, 202A), VID = 400 mVpp (MLVD204A, 205A), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30K samples.
(5) VID = 200 mVpp (MLVD200A, 202A), VID = 400 mVpp (MLVD204A, 205A), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100K samples.
(6) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p))