SCASE17 September   2024 SN74AC2G101

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 CMOS Schmitt-Trigger Inputs
      3. 7.3.3 Latching Logic
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Reference
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC -40°C to 125°C UNIT
MIN MAX
fclock Clock frequency 1.5V 22 MHz
3.3V ± 0.3V 80
5V ± 0.5V 140
6V 175
tW Pulse duration CLR low 1.5V 4.1 ns
3.3V ± 0.3V 3.3
5V ± 0.5V
6V 3.3
CLKx 1.5V 4.1
3.3V ± 0.3V 3.3
5V ± 0.5V
6V 3.3
tSU Set up time D before any CLKx 1.5V 8.3 ns
3.3V ± 0.3V 6.02 ns
5V ± 0.5V
6V 6.02 ns
CLR high before any CLKx 1.5V 8.3 ns
3.3V ± 0.3V 6.02 ns
5V ± 0.5V
6V 6.02 ns
tCLKX_SU Set up time between CLKx inputs CLKA input pin relative to CLKB, CLKC and CLKD pins 1.5V 8.3 ns
3.3V ± 0.3V 6.02 ns
5V ± 0.5V
6V 6.02 ns
CLKB input pin relative to CLKA, CLKC and CLKD pins 1.5V 1 ns
3.3V ± 0.3V 1 ns
5V ± 0.5V
6V 1 ns
CLKC input pin relative to CLKA, CLKB and CLKD pins 1.5V 1 ns
3.3V ± 0.3V 1 ns
5V ± 0.5V
6V 1 ns
CLKD input pin relative to CLKA, CLKB and CLKC pins 1.5V 1 ns
3.3V ± 0.3V 1 ns
5V ± 0.5V
6V 1 ns
tH Hold time D after any CLKx 1.5V 8.3 ns
3.3V ± 0.3V 6.02 ns
5V ± 0.5V
6V 6.02 ns