SCES595N JULY   2004  – July 2017 SN74AUP1G125

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, TA = 25°C
    6. 6.6  Electrical Characteristics, TA = -40°C to +85°C
    7. 6.7  Switching Characteristics, CL = 5 pF
    8. 6.8  Switching Characteristics, CL = 10 pF
    9. 6.9  Switching Characteristics, CL = 15 pF
    10. 6.10 Switching Characteristics, CL = 30 pF
    11. 6.11 Operating Characteristics
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diodes
      4. 8.3.4 Partial Power Down (Ioff)
      5. 8.3.5 Over-voltage Tolerant Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from M Revision (December 2015) to N Revision

  • Added DPW (X2SON) packageGo
  • Deleted Device Comparison table, see Mechanical, Packaging, and Orderable Information section at the end of the data sheetGo
  • Changed Simplified Schematic with a new schematicGo
  • Added column for X2SON (DPW) package and separated columns for DSBGA packages in Pin Functions tableGo
  • Changed values in the Thermal Information table to align with JEDEC standards.Go
  • Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, Partial Power Down (Ioff), and Over-voltage Tolerant InputsGo
  • Added Trace Example and revised Layout GuidelinesGo
  • Added Receiving Notification of Documentation Updates sectionGo

Changes from L Revision (February 2013) to M Revision

  • Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal Information table, Typical Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from K Revision (November 2012) to L Revision

  • Changed Y to Y for pin 4 in DSF Package pin out Go