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Noninverting buffers & drivers

SN74AUP1G125

ACTIVE

Single 0.8-V to 3.6-V low power buffer with 3-state outputs

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Data sheet

SN74AUP1G125

ACTIVE
Data sheet Order now

Product details

Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 1 IOL (max) (mA) 4 Supply current (max) (µA) 0.9 IOH (max) (mA) -4 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 1 IOL (max) (mA) 4 Supply current (max) (µA) 0.9 IOH (max) (mA) -4 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YFP) 6 1.4000000000000001 mm² 1 x 1.4000000000000001 DSBGA (YZP) 5 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 5 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DPW) 5 0.64 mm² 0.8 x 0.8 X2SON (DSF) 6 1 mm² 1 x 1
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4 pF Typical at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    < 10% of VCC
  • Input-Disable Feature Allows Floating Input Conditions
  • Ioff Supports Partial-Power-Down Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.6 ns Maximum at 3.3 V
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4 pF Typical at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    < 10% of VCC
  • Input-Disable Feature Allows Floating Input Conditions
  • Ioff Supports Partial-Power-Down Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.6 ns Maximum at 3.3 V

The SN74AUP1G125 bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.

To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74AUP1G125 bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.

To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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Technical documentation

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Type Title Date
* Data sheet SN74AUP1G125 Low-Power Single Bus Buffer Gate With 3-State Output datasheet (Rev. N) PDF | HTML 10 Jul 2017
Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 22 May 2019
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Application note Designing and Manufacturing with TI's X2SON Packages 23 Aug 2017
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Simulation model

HSPICE Model for SN74AUP1G125

SCEJ267.ZIP (99 KB) - HSpice Model
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Simulation model

SN74AUP1G125 Behavioral SPICE Model

SCEM689.ZIP (7 KB) - PSpice Model
Download
Simulation model

SN74AUP1G125 IBIS Model (Rev. B)

SCEM460B.ZIP (79 KB) - IBIS Model
Download
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Design guide: PDF
Schematic: PDF
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Test report: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
DSBGA (YFP) 6 Ultra Librarian
DSBGA (YZP) 5 Ultra Librarian
SOT-23 (DBV) 5 Ultra Librarian
SOT-5X3 (DRL) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DPW) 5 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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