Refer to the PDF data sheet for device specific package drawings
These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN74HC164 | SOIC (14) | 8.65 mm × 3.91 mm |
PDIP (14) | 19.30 mm × 6.35 mm | |
SO (14) | 10.30 mm × 5.30 mm | |
TSSOP (14) | 5.00 mm × 4.40 mm | |
SN54HC164 | CDIP (14) | 19.94 mm × 6.92 mm |
CFP (14) | 9.21 mm × 6.29 mm | |
LCCC (14) | 9.39 mm × 9.39 mm |
Changes from F Revision (October 2013) to G Revision
Changes from E Revision (November 2010) to F Revision
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN74HC164D | SOIC (14) | 8.65 mm × 3.91 mm |
SN74HC164N | PDIP (14) | 19.30 mm × 6.35 mm |
SN74HC164NS | SO (14) | 10.30 mm × 5.30 mm |
SN74HC164PW | TSSOP (14) | 5.00 mm × 4.40 mm |
SN54HC164J | CDIP (14) | 19.94 mm × 6.92 mm |
SN54HC164W | CFP (14) | 9.21 mm × 6.29 mm |
SN54HC164FK | LCCC (14) | 9.39 mm × 9.39 mm |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
SOIC, PDIP, SO, CDIP, CFP, or TSSOP NO. | NAME | ||
1 | A | I | Gated Serial Input 1 |
2 | B | I | Gated Serial Input 2 |
3 | QA | O | Parallel Output |
4 | QB | O | Parallel Output |
5 | QC | O | Parallel Output |
6 | QD | O | Parallel Output |
7 | GND | - | Ground |
8 | CLK | I | Clock |
9 | CLR | I | Clear 1 Active-Low |
10 | QE | O | Parallel Output |
11 | QF | O | Parallel Output |
12 | QG | O | Parallel Output |
13 | QH | O | Parallel Output |
14 | VCC | — | Power |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
LCCC NO. | NAME | ||
1 | NC | — | No Connect |
2 | A | I | Gated Serial Input 1 |
3 | B | I | Gated Serial Input 2 |
4 | QA | O | Parallel Output |
5 | NC | — | No Connect |
6 | QB | O | Parallel Output |
7 | NC | — | No Connect |
8 | QC | O | Parallel Output |
9 | QD | O | Parallel Output |
10 | GND | — | Ground |
11 | NC | — | No Connect |
12 | CLK | I | Clock |
13 | CLR | I | Clear 1 Active-Low |
14 | QE | O | Parallel Output |
15 | NC | — | No Connect |
16 | QF | O | Parallel Output |
17 | NC | — | No Connect |
18 | QG | O | Parallel Output |
19 | QH | O | Parallel Output |
20 | VCC | — | Power |