SCLS115G December   1982  – September 2015 SN54HC164 , SN74HC164

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics, TA = 25°C
    6. 7.6  Electrical Characteristics, TA = -55°C to 125°C
    7. 7.7  Electrical Characteristics, TA = -55°C to 85°C
    8. 7.8  Timing Requirements, TA = 25°C
    9. 7.9  Timing Requirements, TA = -55°C to 125°C
    10. 7.10 Timing Requirements, TA = -55°C to 85°C
    11. 7.11 Switching Characteristics, TA = 25°C
    12. 7.12 Switching Characteristics, TA = -55°C to 125°C
    13. 7.13 Switching Characteristics, TA = -55°C to 85°C
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • PW|14
  • N|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up to 10 LSTTL Loads
  • Low Power Consumption, 80-μA Maximum ICC
  • Typical tpd = 20 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1-μA Maximum
  • AND-Gated (Enable/Disable) Serial Inputs
  • Fully Buffered Clock and Serial Inputs
  • Direct Clear
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.

2 Applications

  • Programable Logic Controllers
  • Appliances
  • Video Display Systems
  • Output Expander

3 Description

These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74HC164 SOIC (14) 8.65 mm × 3.91 mm
PDIP (14) 19.30 mm × 6.35 mm
SO (14) 10.30 mm × 5.30 mm
TSSOP (14) 5.00 mm × 4.40 mm
SN54HC164 CDIP (14) 19.94 mm × 6.92 mm
CFP (14) 9.21 mm × 6.29 mm
LCCC (14) 9.39 mm × 9.39 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

SN54HC164 SN74HC164 Logic_1.gif