Product details

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 24 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 125 Rating Catalog
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 24 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 125 Rating Catalog
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up to 10 LSTTL Loads
  • Low Power Consumption, 80-µA Maximum ICC
  • Typical tpd = 20 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1-µA Maximum
  • AND-Gated (Enable/Disable) Serial Inputs
  • Fully Buffered Clock and Serial Inputs
  • Direct Clear
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise
    Noted. On All Other Products, Production
    Processing Does Not Necessarily Include
    Testing of All Parameters.
  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up to 10 LSTTL Loads
  • Low Power Consumption, 80-µA Maximum ICC
  • Typical tpd = 20 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1-µA Maximum
  • AND-Gated (Enable/Disable) Serial Inputs
  • Fully Buffered Clock and Serial Inputs
  • Direct Clear
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise
    Noted. On All Other Products, Production
    Processing Does Not Necessarily Include
    Testing of All Parameters.

These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

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Technical documentation

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Type Title Date
* Data sheet SNx4HC164 8-Bit Parallel-Out Serial Shift Registers datasheet (Rev. G) PDF | HTML 03 Feb 2014
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Technical article How to create a dynamic power solution for stepper motors, relays and LEDs PDF | HTML 01 Nov 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note HCMOS Design Considerations (Rev. A) 09 Sep 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Package Pins CAD symbols, footprints & 3D models
PDIP (N) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian

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