SCLS393Q APRIL   1998  – August 2015 SN74LV123A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, VCC = 2.5 V ± 0.2 V
    7. 7.7  Timing Requirements, VCC = 3.3 V ± 0.3 V
    8. 7.8  Timing Requirements, VCC = 5 V ± 0.5 V
    9. 7.9  Switching Characteristics, VCC = 2.5 V ± 0.2 V
    10. 7.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    11. 7.11 Switching Characteristics, VCC = 5 V ± 0.5 V
    12. 7.12 Operating Characteristics
    13. 7.13 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Power-Down Considerations
        2. 10.2.1.2 Output Pulse Duration
        3. 10.2.1.3 Retriggering Data
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

D, DB, DGV, NS, or PW Package
16-Pin SOIC, SSOP, SO, TSSOP
Top View
SN54LV123A SN74LV123A po_j_cls393.gif
RGY Package
16-Pin VQFN
Top View
SN54LV123A SN74LV123A po_rgy_cls393.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
1A 1 I Channel 1 falling edge trigger input when 1B = L; Hold low for other input methods
1B 2 I Channel 1 rising edge trigger input when 1A = H; Hold high for other input methods
1CLR 3 I Channel 1 rising edge trigger when 1A = H and 1B = L; Hold high for other input methods; Can cut pulse length short by driving low during output
1Q 4 O Channel 1 inverted output
2Q 5 O Channel 2 output
2Cext 6 — Channel 2 external capacitor negative connection
2Rext/Cext 7 — Channel 2 external capacitor and resistor junction connection
GND 8 — Ground
2A 9 I Channel 2 falling edge trigger input when 2B = L; Hold low for other input methods
2B 10 I Channel 2 rising edge trigger input when 2A = H; Hold high for other input methods
2CLR 11 I Channel 2 rising edge trigger when 2A = H and 2B = L; Hold high for other input methods; Can cut pulse length short by driving low during output
2Q 12 O Channel 2 inverted output
1Q 13 O Channel 1 output
1Cext 14 — Channel 1 external capacitor negative connection
1Rext/Cext 15 — Channel 1 external capacitor and resistor junction connection
VCC 16 — Power supply