SCLS745D December   2013  – March 2024 SN74LV1T125

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Operating Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clamp Diode Structure
      2. 8.3.2 Balanced CMOS Push-Pull Outputs
      3. 8.3.3 LVxT Enhanced Input Voltage
        1. 8.3.3.1 Down Translation
        2. 8.3.3.2 Up Translation
    4. 8.4 Device Functional Modes
  10. 9 Application Information Disclaimer
    1. 9.1 Layout
      1. 9.1.1 Layout Guidelines
    2. 9.2 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support (Analog)
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4 Device Functional Modes

Function Tables
INPUT (1)
(LOWER LEVEL INPUT)		OUTPUT (2)
(VCC CMOS)
OE(3)AY
LHH
LLL
HXZ
(1) H = High Voltage Level, L = Low Voltage Level, X = Do not Care, Z = High Impedance
(2) H = Driving High, L = Driving Low, Z = High Impedance State
(3) Not recommend to float OE pin for signal oscillation.
SUPPLY VCC = 3.3 V
INPUT
(LOWER LEVEL INPUT)		OUTPUT
(VCC CMOS)
ABY
 VIH(min) = 1.35 V
VIL(max) = 0.8 V		 VOH(min) = 2.9 V
VOL(max) = 0.2 V