SCES340F september 2000 – july 2023 SN74LV21A
PRODMIX
- 1
- 1Features
- 2Description
- 3Revision History
- 4Pin Configuration and Functions
-
5Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics
- 5.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V
- 5.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V
- 5.8 Switching Characteristics, VCC = 5 V ± 0.5 V
- 5.9 Noise Characteristics
- 5.10 Operating Characteristics
- 6Parameter Measurement Information
- 7Detailed Description
- 8Device and Documentation Support
- 9Mechanical, Packaging, and Orderable Information
Package Options
Refer to the PDF data sheet for device specific package drawings
Mechanical Data (Package|Pins)
- D|14
- DB|14
- DGV|14
- PW|14
- NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information
2 Description
These dual 4-input positive-AND gates are designed for 2-V to 5.5-V VCC operation.
The SN74LV21A devices perform the Boolean function Y = A • B • C • D in positive logic.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
Package Information
| PART NUMBER | PACKAGE1 | PACKAGE SIZE2 |
|---|---|---|
| SN74LV21A | DGV (TVSOP, 14) | 3.60 mm x 6.4 mm |
| D (SOIC, 14) | 8.65 mm x 6 mm | |
| NS (SO, 14) | 10.20 mm x 7.8 mm | |
| DB (SSOP, 14) | 6.20 mm x 7.8 mm | |
| PW (TSSOP, 14) | 5.00 mm x 6.4 mm |
(1) For all available packages, see
the orderable addendum at the end of the data sheet.
(2) The package size (length × width)
is a nominal value and includes pins, where applicable.
