SCES424M January   2003  – August 2022 SN74LVC1G3157

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Analog Switch Characteristics
    7. 6.7 Switching Characteristics 85°C
    8. 6.8 Switching Characteristics 125°C
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Switching Characteristics 85°C

TA = –40 to +85°C (see Figure 7-4 and )Figure 7-10
PARAMETERFROM
(INPUT)		TO
(OUTPUT)		VCC = 1.8 V
± 0.15 V		VCC = 2.5 V
± 0.2 V		VCC = 3.3 V
± 0.3 V		VCC = 5 V
± 0.5 V		UNIT
MINMAXMINMAXMINMAXMINMAX
tpd(1)A or BnBn or A21.20.80.3ns
ten(2)SBn7243.5142.57.61.75.7ns
tdis(3)31327.51.55.30.83.8
tB-M0.50.50.50.5ns
(1) tpd is the slower of tPLH or tPHL. The propagation delay is calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance).
(2) ten is the slower of tPZL or tPZH.
(3) tdis is the slower of tPLZ or tPHZ.