SLLS059E February   1990  – February 2024 SN751177 , SN751178

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Thermal Information
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Driver Sections
      1. 5.4.1 Electrical Characteristics
      2. 5.4.2 Switching Characteristics
      3. 5.4.3 Symbol Equivalents
    5. 5.5 Receiver Sections
      1. 5.5.1 Electrical Characteristics
      2. 5.5.2 Switching Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Device Functional Modes
  9. Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NS|16
  • N|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Functional Modes

Table 7-1 SN751177, SN751178 Functional Table (Each Driver)
INPUT D(1) ENABLE DE OUTPUTS
Y Z
H H H L
L H L H
X L Z Z
H = high level, L = low level, X = irrelevant, Z = high impedance (off)
Table 7-2 SN751177 Functional Table (Each Receiver)
DIFFERENTIAL INPUTS A − B ENABLE RE OUTPUT R(1)
VID ≥ 0.2V L H
−0.2V < VID < 0.2V L ?
VID ≤ −0.2V L L
X H Z
Open L H
H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off)
Table 7-3 SN751178 Functional Table (Each Receiver)
DIFFERENTIAL INPUTS A − B OUTPUT R(1)
VID ≥ 0.2V H
−0.2V < VID < 0.2V ?
VID ≤ −0.2V L
H = high level, L = low level, ? = indeterminate
GUID-5E12E588-C671-49EB-998C-B543600007D8-low.png
All resistor values are nominal.
Figure 7-1 Schematics of Inputs
GUID-E7D42CFE-9E85-409C-941A-3570D996C946-low.png
All resistor values are nominal.
Figure 7-2 Schematics of Outputs