SLLS040I August   1987  – January 2023 SN65ALS176 , SN75ALS176 , SN75ALS176A , SN75ALS176B

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Recommended Operating Conditions
    3. 5.3  Thermal Information
    4. 5.4  Electrical Characteristics - Driver
    5. 5.5  Switching Characteristics - Driver
    6. 5.6  Switching Characteristics - Driver
    7. 5.7  Symbol Equivalents
    8. 5.8  Electrical Characteristics - Receiver
    9. 5.9  Switching Characteristics - Receiver
    10. 5.10 Switching Characteristics - Receiver
    11. 5.11 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Switching Characteristics - Driver

SN65ALS176

over recommended ranges of supply voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
td(OD) Differential output delay time RL = 54 Ω CL = 50 pF, See Figure 6-3 15 ns
tsk(p) Pulse skew(2) RL = 54 Ω CL = 50 pF, See Figure 6-3 0 2 ns
tsk(lim) Pulse skew(3) RL = 54 Ω CL = 50 pF, See Figure 6-3 15 ns
tt(OD) Differential output transition time RL = 54 Ω CL = 50 pF, See Figure 6-3 8 ns
tPZH Output enable time to high level RL = 110 Ω CL = 50 pF, See Figure 6-4 80 ns
tPZL Output enable time to low level RL = 110 Ω CL = 50 pF, See Figure 6-5 30 ns
tPHZ Output disable time from high level RL = 110 Ω CL = 50 pF, See Figure 6-4 50 ns
tPLZ Output disable time from low level RL = 110 Ω CL = 50 pF, See Figure 6-5 30 ns
(1) All typical values are at VCC = 5 V, TA = 25°C.
(2) Pulse skew is defined as the |tPLH– tPHL| of each channel of the same device.
(3) Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.