SNLS692B December   2021  – December 2023 SN75LVPE5421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Five-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Flat Gain
      4. 6.3.4 Receiver Detect State Machine
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Active Buffer Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 PCIe x8 Lane Switching
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Protocol Agnostic Linear Redriver for High Speed Interfaces
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUA|42
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.2 SMBUS/I2C Register Control Interface

If MODE = L2 (SMBus / I2C secondary control mode), the SN75LVPE5421 is configured for best signal integrity through a standard I2C or SMBus interface that may operate up to 400 kHz. The secondary address of the SN75LVPE5421 is determined by the pin strap settings on the ADDR and MODE pins. Table 6-5 provides the eight possible secondary addresses (7-bit) for each channel banks of the device. In SMBus/I2C modes the SCL, SDA pins must be pulled up to a 3.3V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7kΩ is a good first approximation for a bus capacitance of 10pF.

Table 6-5 SMBUS/I2C Secondary Address Settings
MODEADDR7-bit Secondary Address Channels 0-17-bit Secondary Address Channels 2-3
L1L00x180x19
L1L10x1A0x1B
L1L20x1C0x1D
L1L30x1E0x1F
X L4 Reserved Reserved
L2L00x200x21
L2L10x220x23
L2L20x240x25
L2L30x260x27

The SN75LVPE5421 has two types of registers:

  • Shared Registers: These registers can be accessed at any time and are used for device-level configuration, status read back, control, or to read back the device ID information.
  • Channel Registers: These registers are used to control and configure specific features for each individual channel. All channels have the same register set and can be configured independent of each other or configured as a group through broadcast writes to Bank 0 or Bank 1.

The SN75LVPE5421 features two banks of channels, Bank 0 (Channels 0-1) and Bank 1 (Channels 2-), each featuring a separate register set and requiring a unique SMBus secondary address.

Channel Registers Base Address Channel Bank 0 Access Channel Bank 1 Access
0x00 Channel 0 registers Channel 2 registers
0x20 Channel 0 registers Channel 2 registers
0x40 Channel 1 registers Channel 3 registers
0x60 Channel 1 registers Channel 3 registers
0x80

Broadcast write channel Bank 0 registers,

read channel 0 registers

Broadcast write channel Bank 1 registers,

read channel 2 registers
0xE0 Bank 0 Share registers Bank 1 Share registers