SNLS692B December   2021  – December 2023 SN75LVPE5421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Five-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Flat Gain
      4. 6.3.4 Receiver Detect State Machine
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Active Buffer Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 PCIe x8 Lane Switching
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Protocol Agnostic Linear Redriver for High Speed Interfaces
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUA|42
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Quad channel PCIe 5.0 linear redriver or repeater with integrated 2:1 multiplexer
  • Protocol agnostic linear redriver compatible to PCIe, UPI, CCIX, NVLink, DisplayPort, SAS, SATA, and XFI
  • Single 3.3V supply – PCIe power rail can be used
  • Low 720mW active power for 4-channel operation
  • No heat sink required
  • Provides equalization up to 24dB at 16GHz
  • Excellent RX/TX differential RL of -10dB for 8-16GHz
  • Low additive RJ of 55 fs RMS with PRBS data
  • Low latency of 90ps
  • Automatic receiver detection and seamless support for PCIe link training
  • Device configuration by pin control or SMBus / I2C.
  • Mux selection through pin
  • Internal voltage regulator provides immunity to supply noise
  • High speed production testing for reliable manufacturing
  • Support for x4, x8, and x16 bus width with one or multiple device
  • Available companion demultiplexer product SN75LVPE5412
  • -40°C to 85°C temperature range
  • 3.5 × 9mm 42 Pin 0.5mm pitch WQFN package