SLASF30A January   2022  – December 2024 TAA5212

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI Interface
    9. 5.9  Switching Characteristics: SPI Interface
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digital Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3  Input Channel Configurations
      4. 6.3.4  Reference Voltage
      5. 6.3.5  Programmable Microphone Bias
      6. 6.3.6  Signal-Chain Processing
        1. 6.3.6.1 ADC Signal-Chain
          1. 6.3.6.1.1  6 to 4 Input Select Multiplexer (6:4 MUX)
          2. 6.3.6.1.2  Programmable Channel Gain and Digital Volume Control
          3. 6.3.6.1.3  Programmable Channel Gain Calibration
          4. 6.3.6.1.4  Programmable Channel Phase Calibration
          5. 6.3.6.1.5  Programmable Digital High-Pass Filter
          6. 6.3.6.1.6  Programmable Digital Biquad Filters
          7. 6.3.6.1.7  Programmable Channel Summer and Digital Mixer
          8. 6.3.6.1.8  Configurable Digital Decimation Filters
            1. 6.3.6.1.8.1 Linear-phase filters
              1. 6.3.6.1.8.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.6.1.8.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.6.1.8.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.6.1.8.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.6.1.8.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.6.1.8.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.6.1.8.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.6.1.8.2 Low-latency Filters
              1. 6.3.6.1.8.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.6.1.8.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.6.1.8.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.6.1.8.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.6.1.8.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.6.1.8.3 Ultra Low-latency Filters
              1. 6.3.6.1.8.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.6.1.8.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.6.1.8.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.6.1.8.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.6.1.8.3.5 Sampling Rate: 192kHz or 176.4kHz
          9. 6.3.6.1.9  Automatic Gain Controller (AGC)
          10. 6.3.6.1.10 Voice Activity Detection (VAD)
          11. 6.3.6.1.11 Ultrasonic Activity Detection (UAD)
      7. 6.3.7  Digital PDM Microphone Record Channel
      8. 6.3.8  Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9  Power Tune Mode
      10. 6.3.10 Incremental ADC (IADC) Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAA5212_B0_P0 Registers
      2. 7.1.2 TAA5212_B0_P1 Registers
      3. 7.1.3 TAA5212_B0_P3 Registers
    2. 7.2 Programmable Coefficienct Registers
      1. 7.2.1 Programmable Coefficient Registers: Page 8
      2. 7.2.2 Programmable Coefficient Registers: Page 9
      3. 7.2.3 Programmable Coefficient Registers: Page 10
      4. 7.2.4 Programmable Coefficient Registers: Page 11
      5. 7.2.5 Programmable Coefficient Registers: Page 19
      6. 7.2.6 Programmable Coefficient Registers: Page 27
      7. 7.2.7 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Example Device Register Configuration Scripts for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD_MODE for 1.8V Operation
      2. 8.3.2 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.7 Digital PDM Microphone Record Channel

In addition to supporting analog microphones, the TAA5212 also interfaces to digital pulse-density-modulation (PDM) microphones and uses high-order and high-performance decimation filters to generate pulse code modulation (PCM) output data that can be transmitted on the audio serial interface to the host. The device supports up to four digital microphone recording channels (when the analog channels are not used). The device can also support simultaneous recording on two analog and two digital microphone channels or one analog channel and three digital microphone channels.

The GPIOx, GPI1 and GPO1 pins can be configured for the PDM data lines (PDMDINx) and PDM Clock (PDMCLK) functions as per the Table 6-41 for the digital PDM microphone recording.

The device internally generates PDMCLK with a programmable frequency of either 6.144MHz, 3.072MHz, 1.536MHz, or 768kHz (for output data sample rates in multiples or submultiples of 48kHz) or 5.6448MHz, 2.8224MHz, 1.4112MHz, or 705.6kHz (for output data sample rates in multiples or submultiples of 44.1kHz) using the PDM_CLK_CFG[1:0] (P0_R53_D[7:6]) register bits. PDMCLK can be routed on the GPIOx and GPO1 pins using the respective configuration registers: GPIO1_CFG (P0_R10[7:4]), GPIO2_CFG (P0_R11[7:4]) and GPO1_CFG (P0_R12[7:4]). This clock can be connected to the external digital microphone device. Figure 6-63 shows a connection diagram of the digital PDM microphones.

TAA5212 Digital PDM Microphones Connection Diagram for the TAA5212 Figure 6-63 Digital PDM Microphones Connection Diagram for the TAA5212

The single-bit output of the external digital microphone device can be connected to the GPI1 or GPIOx pin. The device supports two PDM data lines: PDMDIN1 and PDMDIN2 set through the registers PDM_DIN1_SEL (P0_R19_D[3:2]) and PDM_DIN2_SEL (P0_R19_D[1:0]). When using GPI1, make sure that the GPI1 function is enabled using the GPI1_CFG (P0_R13[1]). This single data line can be shared by two digital microphones to place their data on the opposite edge of PDMCLK. Internally, the device latches the steady value of the data on either the rising or falling edge of PDMCLK based on the configuration register bits set in PDMDIN1_EDGE (P0_R19_D[4]) and PDMDIN2_EDGE (P0_R19_D[5]). Figure 6-64 shows the digital PDM microphone interface timing diagram.

TAA5212 Digital PDM Microphone Protocol Timing Diagram Figure 6-64 Digital PDM Microphone Protocol Timing Diagram

When the digital microphone is used for recording, the analog blocks of the respective ADC channel are powered down and bypassed for power efficiency. Channel 3 and channel 4 support only the digital microphone interface. Use the PDM_CH1_SEL[1:0] (P0_R19_D[7]) and PDM_CH2_SEL[1:0] (P0_R19_D[6]) register bits to select the analog microphone or digital microphone for channel 1 to channel 2 respectively.