SLASF30A January   2022  – December 2024 TAA5212

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI Interface
    9. 5.9  Switching Characteristics: SPI Interface
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digital Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3  Input Channel Configurations
      4. 6.3.4  Reference Voltage
      5. 6.3.5  Programmable Microphone Bias
      6. 6.3.6  Signal-Chain Processing
        1. 6.3.6.1 ADC Signal-Chain
          1. 6.3.6.1.1  6 to 4 Input Select Multiplexer (6:4 MUX)
          2. 6.3.6.1.2  Programmable Channel Gain and Digital Volume Control
          3. 6.3.6.1.3  Programmable Channel Gain Calibration
          4. 6.3.6.1.4  Programmable Channel Phase Calibration
          5. 6.3.6.1.5  Programmable Digital High-Pass Filter
          6. 6.3.6.1.6  Programmable Digital Biquad Filters
          7. 6.3.6.1.7  Programmable Channel Summer and Digital Mixer
          8. 6.3.6.1.8  Configurable Digital Decimation Filters
            1. 6.3.6.1.8.1 Linear-phase filters
              1. 6.3.6.1.8.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.6.1.8.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.6.1.8.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.6.1.8.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.6.1.8.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.6.1.8.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.6.1.8.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.6.1.8.2 Low-latency Filters
              1. 6.3.6.1.8.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.6.1.8.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.6.1.8.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.6.1.8.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.6.1.8.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.6.1.8.3 Ultra Low-latency Filters
              1. 6.3.6.1.8.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.6.1.8.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.6.1.8.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.6.1.8.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.6.1.8.3.5 Sampling Rate: 192kHz or 176.4kHz
          9. 6.3.6.1.9  Automatic Gain Controller (AGC)
          10. 6.3.6.1.10 Voice Activity Detection (VAD)
          11. 6.3.6.1.11 Ultrasonic Activity Detection (UAD)
      7. 6.3.7  Digital PDM Microphone Record Channel
      8. 6.3.8  Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9  Power Tune Mode
      10. 6.3.10 Incremental ADC (IADC) Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAA5212_B0_P0 Registers
      2. 7.1.2 TAA5212_B0_P1 Registers
      3. 7.1.3 TAA5212_B0_P3 Registers
    2. 7.2 Programmable Coefficienct Registers
      1. 7.2.1 Programmable Coefficient Registers: Page 8
      2. 7.2.2 Programmable Coefficient Registers: Page 9
      3. 7.2.3 Programmable Coefficient Registers: Page 10
      4. 7.2.4 Programmable Coefficient Registers: Page 11
      5. 7.2.5 Programmable Coefficient Registers: Page 19
      6. 7.2.6 Programmable Coefficient Registers: Page 27
      7. 7.2.7 Programmable Coefficient Registers: Page 28
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Example Device Register Configuration Scripts for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD_MODE for 1.8V Operation
      2. 8.3.2 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Input Channel Configurations

The TAA5212 consists of two pairs of analog input pins (INxP and INxM) that can be configured as differential inputs or single-ended inputs for the recording channels. The device supports simultaneous recording of up to two analog channels using the high-performance multichannel ADC. The input source for the analog pins can be from electret condenser analog microphones, microelectrical-mechanical system (MEMS) analog microphones, or line-in (auxiliary) inputs from the system board. Analog inputs support differential inputs and single-ended inputs with AC and DC coupling options.

Table 6-9 shows the input configuration for the record channel 1.

Table 6-9 Input Source Selection for the Record Channel
P0_R80_D[7:6] : ADC_CH1_INSRC[1:0] INPUT CHANNEL 1 CONFIGURATION
00 (default) Analog differential input for channel 1 using IN1P and IN1M
01 Analog single-ended input for channel 1 using IN1P and IN1M (signal on one input pin and ground on other pin)
10 Analog single-ended input mux on IN1P (signal on one input pin and no additional ground pin required)
11 Analog single-ended input mux on IN1M (signal on one input pin and no additional ground pin required)
Similarly, the input configuration setting for input channel 2 can be configured using the ADC_CH2_INSRC[1:0] (P0_R85_D[7:6]) register bits.

Typically, voice or audio signal inputs are capacitively coupled (AC-coupled) to the device and the common-mode variation at the device input is limited to less than 100mVpp for differential inputs. However, for applications that cannot avoid large common-mode fluctuations or when needed to save board space, the device also supports options for increasing the common mode tolerance and for DC-coupled inputs. This configuration can be done independently for each channel by setting the input common mode tolerance in ADC_CH1_CM_TOL (P0_R80_D[3:2]) and ADC_CH2_CM_TOL (P0_R85_D[3:2]) register bits. Table 6-9 shows these options for Channel 1. Setting higher common mode tolerance offers improved CMRR performance at the expense of noise performance by a few decibels.

Table 6-10 Input Common Mode Tolerance for the Record Channel
P0_R80_D[3:2] : ADC_CH1_CM_TOL[1:0] INPUT CHANNEL 1 COMMON MODE TOLERANCE
00 (default) AC-coupled input with common mode variance tolerance supported 50mVpp for single ended and 100mVpp for differential configuration
01 AC-coupled / DC-coupled input with common mode variance tolerance supported 500mVpp for single ended and 1Vpp for differential configuration
10 AC-coupled / DC-coupled input with common mode variance tolerance supported rail to rail (supply to ground) (High CMRR tolerance mode)
11 Reserved

See Figure 6-15 to Figure 6-18) for the various typical input configuration diagrams. For single-ended inputs, the INxM pin can be directly grounded in DC-coupled configuration, but the INxM pin must be grounded after the AC-coupling capacitor in the AC-coupled configuration. For the best dynamic range performance, the differential AC-coupled input setting should be used and the common-mode variation at the device input should be limited to less than 100mVpp. For more details, refer Analog Input Configurations, Mixing and Muxing of TAx5x1x Devices application report.
TAA5212 Differential AC-Coupled Input
                                                Connection (ADC_CHx_INSRC set to 2'b00 and
                                                ADC_CHx_CM_TOL set to 2'b00 or 2'b01 or
                                                2'10)Figure 6-15 Differential AC-Coupled Input Connection (ADC_CHx_INSRC set to 2'b00 and ADC_CHx_CM_TOL set to 2'b00 or 2'b01 or 2'10)
TAA5212 Single-ended AC-Coupled Input
                                                Connection (ADC_CHx_INSRC set to 2'b01 and
                                                ADC_CHx_CM_TOL set to 2'b00 or 2'b01 or
                                                2'10)Figure 6-17 Single-ended AC-Coupled Input Connection (ADC_CHx_INSRC set to 2'b01 and ADC_CHx_CM_TOL set to 2'b00 or 2'b01 or 2'10)
TAA5212 Single-ended mux on INxP
                                                AC-Coupled Input Connection (ADC_CHx_INSRC set to
                                                2'b10 and ADC_CHx_CM_TOL set to 2'b00 or 2'b01 or
                                                2'10)Figure 6-19 Single-ended mux on INxP AC-Coupled Input Connection (ADC_CHx_INSRC set to 2'b10 and ADC_CHx_CM_TOL set to 2'b00 or 2'b01 or 2'10)
TAA5212 Differential DC-Coupled Input
                                                Connection (ADC_CHx_INSRC set to 2'b00 and
                                                ADC_CHx_CM_TOL set to 2'b01 or 2'10)Figure 6-16 Differential DC-Coupled Input Connection (ADC_CHx_INSRC set to 2'b00 and ADC_CHx_CM_TOL set to 2'b01 or 2'10)
TAA5212 Single-ended DC-Coupled Input
                                                Connection (ADC_CHx_INSRC set to 2'b01 and
                                                ADC_CHx_CM_TOL set to 2'b01 or 2'10)Figure 6-18 Single-ended DC-Coupled Input Connection (ADC_CHx_INSRC set to 2'b01 and ADC_CHx_CM_TOL set to 2'b01 or 2'10)
TAA5212 Single-ended mux on INxP
                                                DC-Coupled Input Connection (ADC_CHx_INSRC set to
                                                2'b10 and ADC_CHx_CM_TOL set to 2'b01 or
                                                2'10)Figure 6-20 Single-ended mux on INxP DC-Coupled Input Connection (ADC_CHx_INSRC set to 2'b10 and ADC_CHx_CM_TOL set to 2'b01 or 2'10)

The device also allows for flexibility in choosing the typical input impedance on INxP or INxM from 5kΩ (default), 10kΩ, and 40kΩ based on the input source impedance selection. There can be a ±20% variation on the selected input impedance value. The higher input impedance results in slightly higher noise or lower dynamic range. Table 6-11 lists the configuration register settings for the input impedance for the record channel.

Table 6-11 Input Impedance Selection for the Record Channel
P0_R80_D[5:4] : ADC_CH1_IMP[1:0] CHANNEL 1 INPUT IMPEDANCE SELECTION
00 (default) Channel 1 input impedance typical value is 5 kΩ on INxP or INxM
01 Channel 1 input impedance typical value is 10 kΩ on INxP or INxM
10 Channel 1 input impedance typical value is 40 kΩ on INxP or INxM
11 Reserved (do not use this setting)

Similarly, the input impedance selection setting for input channel 2 can be configured using the ADC_CH2_IMP[1:0] (P0_R85_D[5:4]). Input impedance setting of 5 kΩ is not supported when the ADC inputs are configured for single ended mux (ADC_CHx_INSRC = 2'b10 or 2'b11) and also not supported in the high swing mode (Section 6.3.4).

The value of the coupling capacitor in AC-coupled mode must be chosen so that the high-pass filter formed by the coupling capacitor and the input impedance do not affect the desired low frequency signal bandwidth and amplitude. Before proper recording can begin, this coupling capacitor must be charged up to the common-mode voltage at power-up. To enable quick charging, the device has modes to speed up the charging of the coupling capacitor. The default value of the quick-charge timing is set for a coupling capacitor up to 1µF. However, if a higher-value capacitor is used in the system, then the quick-charging timing can be increased by using the INCAP_QCHG (P0_R5_D[7:6]) register bits. For low distortion performance, use of low-voltage coefficient capacitors for AC coupling is recommended.

If the application uses digital PDM microphones for the recording, GPIOx, GPI1 and GPO1 pins can be reconfigured in the device to support up to four channels for the digital microphone recording (when the analog channels are not used). The device can also support simultaneous recording on two analog and two digital microphone channels or one analog channel and three digital microphone channels. Section 6.3.7 describes more details on the Digital PDM Microphone Record Channel.

The TAA5212 also supports incremental mode of ADC where the analog input channels can be used for DC measurements. This can be configured by setting the IADC_EN (P0_R81_D[7]). For more details on the incremental mode of ADC, refer Section 6.3.10.