SLASF30A January 2022 – December 2024 TAA5212
PRODUCTION DATA
The TAA5212 consists of two pairs of analog input pins (INxP and INxM) that can be configured as differential inputs or single-ended inputs for the recording channels. The device supports simultaneous recording of up to two analog channels using the high-performance multichannel ADC. The input source for the analog pins can be from electret condenser analog microphones, microelectrical-mechanical system (MEMS) analog microphones, or line-in (auxiliary) inputs from the system board. Analog inputs support differential inputs and single-ended inputs with AC and DC coupling options.
Table 6-9 shows the input configuration for the record channel 1.
P0_R80_D[7:6] : ADC_CH1_INSRC[1:0] | INPUT CHANNEL 1 CONFIGURATION |
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00 (default) | Analog differential input for channel 1 using IN1P and IN1M |
01 | Analog single-ended input for channel 1 using IN1P and IN1M (signal on one input pin and ground on other pin) |
10 | Analog single-ended input mux on IN1P (signal on one input pin and no additional ground pin required) |
11 | Analog single-ended input mux on IN1M (signal on one input pin and no additional ground pin required) |
Typically, voice or audio signal inputs are capacitively coupled (AC-coupled) to the device and the common-mode variation at the device input is limited to less than 100mVpp for differential inputs. However, for applications that cannot avoid large common-mode fluctuations or when needed to save board space, the device also supports options for increasing the common mode tolerance and for DC-coupled inputs. This configuration can be done independently for each channel by setting the input common mode tolerance in ADC_CH1_CM_TOL (P0_R80_D[3:2]) and ADC_CH2_CM_TOL (P0_R85_D[3:2]) register bits. Table 6-9 shows these options for Channel 1. Setting higher common mode tolerance offers improved CMRR performance at the expense of noise performance by a few decibels.
P0_R80_D[3:2] : ADC_CH1_CM_TOL[1:0] | INPUT CHANNEL 1 COMMON MODE TOLERANCE |
---|---|
00 (default) | AC-coupled input with common mode variance tolerance supported 50mVpp for single ended and 100mVpp for differential configuration |
01 | AC-coupled / DC-coupled input with common mode variance tolerance supported 500mVpp for single ended and 1Vpp for differential configuration |
10 | AC-coupled / DC-coupled input with common mode variance tolerance supported rail to rail (supply to ground) (High CMRR tolerance mode) |
11 | Reserved |
The device also allows for flexibility in choosing the typical input impedance on INxP or INxM from 5kΩ (default), 10kΩ, and 40kΩ based on the input source impedance selection. There can be a ±20% variation on the selected input impedance value. The higher input impedance results in slightly higher noise or lower dynamic range. Table 6-11 lists the configuration register settings for the input impedance for the record channel.
P0_R80_D[5:4] : ADC_CH1_IMP[1:0] | CHANNEL 1 INPUT IMPEDANCE SELECTION |
---|---|
00 (default) | Channel 1 input impedance typical value is 5 kΩ on INxP or INxM |
01 | Channel 1 input impedance typical value is 10 kΩ on INxP or INxM |
10 | Channel 1 input impedance typical value is 40 kΩ on INxP or INxM |
11 | Reserved (do not use this setting) |
Similarly, the input impedance selection setting for input channel 2 can be configured using the ADC_CH2_IMP[1:0] (P0_R85_D[5:4]). Input impedance setting of 5 kΩ is not supported when the ADC inputs are configured for single ended mux (ADC_CHx_INSRC = 2'b10 or 2'b11) and also not supported in the high swing mode (Section 6.3.4).
The value of the coupling capacitor in AC-coupled mode must be chosen so that the high-pass filter formed by the coupling capacitor and the input impedance do not affect the desired low frequency signal bandwidth and amplitude. Before proper recording can begin, this coupling capacitor must be charged up to the common-mode voltage at power-up. To enable quick charging, the device has modes to speed up the charging of the coupling capacitor. The default value of the quick-charge timing is set for a coupling capacitor up to 1µF. However, if a higher-value capacitor is used in the system, then the quick-charging timing can be increased by using the INCAP_QCHG (P0_R5_D[7:6]) register bits. For low distortion performance, use of low-voltage coefficient capacitors for AC coupling is recommended.
If the application uses digital PDM microphones for the recording, GPIOx, GPI1 and GPO1 pins can be reconfigured in the device to support up to four channels for the digital microphone recording (when the analog channels are not used). The device can also support simultaneous recording on two analog and two digital microphone channels or one analog channel and three digital microphone channels. Section 6.3.7 describes more details on the Digital PDM Microphone Record Channel.
The TAA5212 also supports incremental mode of ADC where the analog input channels can be used for DC measurements. This can be configured by setting the IADC_EN (P0_R81_D[7]). For more details on the incremental mode of ADC, refer Section 6.3.10.