SLASEG6 Data sheet

SLASEG6B May 2018 – June 2020 TAS3251

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

DKQ|56
- MPDS378A

Thermal pad, mechanical data (Package|Pins)

DKQ|56
- PPTD343

Orderable Information

slaseg6b_oa

8.3.4.3.1 Clock Generation Using the PLL

The TAS3251 device supports a wide range of options to generate the required clocks as shown in Figure 22.

The clocks for the PLL require a source reference clock. This clock is sourced as the incoming SCLK or MCLK, a GPIO can also be used.

The source reference clock for the PLL reference clock is selected by programming the SRCREF value on P0-R13, D[6:4]. The TAS3251 device provides several programmable clock dividers to achieve a variety of sampling rates. See Figure 22.

If PLL functionality is not required, set the PLLEN value on P0-R4, D[0] to 0. In this situation, an external master clock is required.

Table 4. PLL Configuration Registers

CLOCK MULTIPLEXER
REGISTER	FUNCTION	BITS
SREF	PLL Reference	B0-P0-R13-D[6:4]
DDSP	clock divider	B0-P0-R27-D[6:0]
DSCLK	External SCLK Div	B0-P0-R32-D[6:0]
DLRK	External LRCK/FS Div	B0-P0-R33-D[7:0]