SLES239A November   2008  – December 2016 TAS5352A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Audio Specifications (BTL)
    7. 6.7 Audio Specifications (Single-Ended Output)
    8. 6.8 Audio Specifications (PBTL)
    9. 6.9 Typical Characteristics
      1. 6.9.1 BTL Configuration
      2. 6.9.2 SE Configuration
      3. 6.9.3 PBTL Configuration
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 System Power-Up and Power-Down Sequence
        1. 7.3.1.1 Powering Up
        2. 7.3.1.2 Powering Down
      2. 7.3.2 Mid Z Sequence Compatibility
      3. 7.3.3 Error Reporting
      4. 7.3.4 Device Protection System
        1. 7.3.4.1 Use of TAS5352A in High-Modulation-Index Capable Systems
        2. 7.3.4.2 Overcurrent (OC) Protection With Current Limiting and Overload Detection
        3. 7.3.4.3 Pin-to-Pin Short-Circuit Protection (PPSC)
        4. 7.3.4.4 Overtemperature Protection
        5. 7.3.4.5 Undervoltage Protection (UVP) and Power-On-Reset (POR)
      5. 7.3.5 Device Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Protection MODE Selection Pins
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 BTL Application With AD Modulation Filters - 2N
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 PCB Material Recommendation
          2. 8.2.1.2.2 PVDD Capacitor Recommendation
          3. 8.2.1.2.3 Decoupling Capacitor Recommendations
        3. 8.2.1.3 Application Curves
      2. 8.2.2 BTL Application With AD Modulation Filters - 1N
        1. 8.2.2.1 Design Requirements
      3. 8.2.3 SE Application
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
      4. 8.2.4 PBTL Application With AD Modulation Filters
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Application Curves
      5. 8.2.5 Non-Differential PBTL Application
        1. 8.2.5.1 Design Requirements
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TAS5352A can be configured either in stereo BTL mode, 4 channel SE mode, or mono PBTL mode, depending on output power conditions and system design.

8.2 Typical Applications

8.2.1 BTL Application With AD Modulation Filters – 2N

TAS5352A diff_btl_les239.gif Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters

8.2.1.1 Design Requirements

Table 5 lists the design requirements for this example.

Table 5. Design Requirements for Typical Differential BTL

DESIGN PARAMETER EXAMPLE
Low Power (Pullup) Supply 3.3 V
Mid Power Supply (GVDD, VDD) 12 V
High Power Supply (PVDD) 12 – 36 V
PWM Inputs INPUT A = 0 – 3.3 V PWM
INPUT_B = 0 – 3.3 V PWM
INPUT_C = 0 – 3.3 V PWM
INPUT_D = 0 – 3.3 V PWM
Speaker Impedance 4 – 8 Ω

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 PCB Material Recommendation

FR-4 Glass Epoxy material with 2-oz. (70-μm) copper is recommended when using the TAS5352A. The use of this material can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB trace inductance).

8.2.1.2.2 PVDD Capacitor Recommendation

The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These capacitors should be selected for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well designed system power supply, 1000-μF, 50-V capacitors will support more applications. The PVDD capacitors should be low-ESR type because they are used in a circuit associated with high-speed switching.

8.2.1.2.3 Decoupling Capacitor Recommendations

To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio performance, good-quality decoupling capacitors should be used. In practice, X7R should be used in this application.

The voltage of the decoupling capacitors should be selected in accordance with good design practices. Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the selection of the 0.1 μF that is placed on the power supply to each half-bridge. It must withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple current created by high power output. A minimum voltage rating of 50 V is required for use with a 34.5-V power supply.

Detailed information regarding LC filter design and the impact on amplifier performance can be found in the application note LC Filter Design (SLAA701).

8.2.1.3 Application Curves

Relevant performance plots for TAS5352A in BTL configuration are shown in BTL Configuration.

Table 6. Relevant Performance Plots, BTL Configuration

PLOT TITLE FIGURE NUMBER
Total Harmonic Distortion + Noise vs. Output power Figure 1
Output Power vs. Supply Voltage Figure 2
Unclipped Output Power vs. Supply Voltage Figure 3
System Efficiency vs. Output Power Figure 4
System Power Loss vs. Output Power Figure 5
System Output Power vs. Case Temperature Figure 6
Noise Amplitude vs. Frequency Figure 7

8.2.2 BTL Application With AD Modulation Filters – 1N

TAS5352A nondiff_btl_les239.gif Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters

8.2.2.1 Design Requirements

Table 7 lists the design requirements for this example.

Table 7. Design Requirements for Typical Non-Differential BTL

DESIGN PARAMETER EXAMPLE
Low Power (Pullup) Supply 3.3 V
Mid Power Supply (GVDD, VDD) 12 V
High Power Supply (PVDD) 12 – 36 V
PWM Inputs INPUT A = 0 – 3.3 V PWM
INPUT_B = N/C
INPUT_C = 0 – 3.3 V PWM
INPUT_D = N/C
Speaker Impedance 4 – 8 Ω

8.2.3 SE Application

TAS5352A typ_se_les239.gif Figure 16. Typical SE Application

8.2.3.1 Design Requirements

Table 8 lists the design requirements for this example.

Table 8. Design Requirements for Typical SE

DESIGN PARAMETER EXAMPLE
Low Power (Pullup) Supply 3.3 V
Mid Power Supply (GVDD, VDD) 12 V
High Power Supply (PVDD) 12 – 36 V
PWM Inputs INPUT A = 0 – 3.3 V PWM
INPUT_B = 0 – 3.3 V PWM
INPUT_C = 0 – 3.3 V PWM
INPUT_D = 0 – 3.3 V PWM
Speaker Impedance 3 – 4 Ω

8.2.3.2 Application Curves

Relevant performance plots for TAS5352A in SE configuration are shown in SE Configuration.

Table 9. Relevant Performance Plots, SE Configuration

PLOT TITLE FIGURE NUMBER
Total Harmonic Distortion + Noise vs. Output Power Figure 8
Output Power vs. Supply Voltage Figure 9
Power Output vs. Case Temperature Figure 10

8.2.4 PBTL Application With AD Modulation Filters

TAS5352A diff_pbtl_les239_jh.gif Figure 17. Typical Differential (2N) PBTL Application With AD Modulation Filters

8.2.4.1 Design Requirements

Table 10 lists the design requirements for this example.

Table 10. Design Requirements for Typical Differential PBTL

DESIGN PARAMETER EXAMPLE
Low Power (Pullup) Supply 3.3 V
Mid Power Supply (GVDD, VDD) 12 V
High Power Supply (PVDD) 12 – 36 V
PWM Inputs INPUT A = 0 – 3.3 V PWM
INPUT_B = 0 – 3.3 V PWM
INPUT_C = N/C
INPUT_D = 3.3 V PWM
Speaker Impedance 2 – 3 Ω

8.2.4.2 Application Curves

Relevant performance plots for TAS5352A in PBTL configuration are shown in PBTL Configuration.

Table 11. Relevant Performance Plots, PBTL Configuration

PLOT TITLE FIGURE NUMBER
Total Harmonic Distortion + Noise vs. Output Power Figure 11
Output Power vs. Supply Voltage Figure 12
Power Output vs. Case Temperature Figure 13

8.2.5 Non-Differential PBTL Application

TAS5352A nondiff_pbtl_les239_jh.gif Figure 18. Typical Non-Differential (1N) PBTL Application

8.2.5.1 Design Requirements

Table 12 lists the design requirements for this example.

Table 12. Design Requirements for Typical Non-Differential PBTL

DESIGN PARAMETER EXAMPLE
Low Power (Pullup) Supply 3.3 V
Mid Power Supply (GVDD, VDD) 12 V
High Power Supply (PVDD) 12 – 36 V
PWM Inputs INPUT A = 0 – 3.3 V PWM
INPUT_B = N/C
INPUT_C = N/C
INPUT_D = GND
Speaker Impedance 2 – 3 Ω

8.3 System Example

Figure 19 shows a block diagram for a typical audio system using the TAS5352A. The TAS5518 is an 8-channel digital audio PWM processor.

TAS5352A b0047-02_les204_jh.gif Figure 19. Typical System Block Diagram