10.1 Layout Guidelines

• The EVM layout optimizes for low noise and EMC performance.
• The TAS5414C device has a thermal pad up, therefore a the layout must take into account an external heatsink.
• Layout also affects EMC performance.
• The EVM PCB illustrations form the basis for the layout discussions.

10.2 Layout Example

The areas indicated by the label "A", are critical to proper operation and EMC layout. The PVDD and ground decoupling capacitors should be close to the device. These decoupling capacitors must be on both groups of PVDD pins to ground. The ground connections of the snubber circuits must also be close to the grounds of the device. The grounds of the decoupling caps and the snubber circuits do not pass through vias before connecting to the device ground. This reduces the ground impedance for EMC mititgation.

Figure 39. Top Layer

The area referenced as "B" are nets in the PCB layout that have large high frequency switching signals. These should be buried on an inner layer with ground planes on layers above and below to mitigate EMC.

Figure 40. A Mid Layer

The bottom layer in the EVM is almost all ground plane. It can be seen that the other layers have ground planes that fill unused areas. All these ground planes need to be connected together through many vias to reduce the impedance between the ground layers. This allows for reduced EMI.

Figure 41. Bottom Layer

10.3 Thermal Consideration

The design of the thermally augmented package is for interface directly to heat sinks using a thermal interface compound (for example, Arctic Silver, Ceramique thermal compound). The heat sink then absorbs heat from the ICs and couples it to the local air. With proper thermal management this process can reach equilibrium at a lower temperature and heat can be continually removed from the ICs. Because of the device efficiency, heat sinks can be smaller than those required for linear amplifiers of equivalent performance.

R_θJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with the following components:

• R_θJC (the thermal resistance from junction to case, or in this case the heat slug)
• Thermal resistance of the thermal grease
• Thermal resistance of the heat sink

One can calculate the thermal resistance of the thermal grease from the exposed heat slug area and the manufacturer's value for the area thermal resistance of the thermal grease (expressed in °C-in²/W or °C-mm²/W). The area thermal resistance of the example thermal grease with a 0.001-inch (0.0254-mm) thick layer is about 0.007°C-in²/W (4.52°C-mm²/W). The approximate exposed heat slug size is as follows:

Dividing the example area thermal resistance of the thermal grease by the area of the heat slug gives the actual resistance through the thermal grease:

The thermal resistance of thermal pads is generally considerably higher than a thin thermal-grease layer. Thermal tape has an even higher thermal resistance and should not be used at all. The heat-sink vendor generally predicts heat sink thermal resistance, either modeled using a continuous-flow dynamics (CFD) model, or measured.

Thus, for a single monaural channel in the IC, the system R_θJA = R_θJC + thermal-grease resistance + heat-sink resistance.

Table 25 indicates modeled parameters for one device on a heat sink. The junction temperature setting is at 115°C while delivering 20 watts per channel into 4-Ω loads with no clipping. The assumed thickness of the thermal grease is about 0.001 inches (0.0254 mm).

10.4 Electrical Connection of Heat Slug and Heat Sink

Electrically connect the heat sink attached to the heat slug of the device to GND, or leave it floating. Do not connect the heat slug to any other electrical node.

10.5 EMI Considerations

EMI performance depends on both careful integrated circuit design and good system-level design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the design.

The design has minimal parasitic inductances due to the short leads on the package. This dramatically reduces the EMI that results from current passing from the die to the system PCB. Each channel also operates at a different phase. The phase between channels is I²C selectable to either 45° or 180°, to reduce EMI caused by high-current switching. The design also incorporates circuitry that optimizes output transitions that cause EMI.