7.3.1 Adjustable I²C Address

The TAS5720L/M device has two address pins, which allow up to 8 I²C addressable devices to share a common TDM bus. Table 2 lists each I²C Device ID setting.

Use a 22-kΩ resistor with a 5% (or better) tolerance to operate as a pull-up or pull-down resistor. By default, the device uses the TDM time slot equal to the offset from the base I²C Device ID (see Table 2). The TDM slot can also be manually configured by setting the TDM_CFG_SRC bit high (bit 6, reg 0x02) and programming the TDM_SLOT_SELECT[2:0] bits to the desired slot (bits 0-2, reg 0x03).

For 2-channel, I²S operation, TDM slots 0 and 1 correspond to right and left channels respectively. For left and right justified formats, TDM slots 0 and 1 correspond to left and right channels respectively.

7.3.2 I²C Interface

The TAS5720L/M device has a bidirectional I²C interface that is compatible with the Inter-Integrated Circuit (I²C) bus protocol and supports both 100-kHz and 400-kHz data transfer rates. This slave-only device does not support a multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the device and to read device status.

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock (SCL) is "HIGH" to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. The conditions are shown in Figure 39. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5720L/M device holds SDA "LOW" during the acknowledge clock period to indicate an acknowledgment. When this hold occurs, the master transmits the next byte of the sequence. All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and SCL signals to set the "HIGH" level for the bus.

Figure 39. Typical I²C Timing Sequence

Any number of bytes can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 39.

7.3.2.1 Writing to the I²C Interface

As shown Figure 40, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I²C bit and the read/write bit. The read/write bit determines the direction of the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I²C bit and the read/write bit, the TAS5720L/M device responds with an acknowledge bit. Next, the master transmits the address byte corresponding to the TAS5720L/M device register being accessed. After receiving the address byte, the TAS5720L/M device again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5720L/M device again responds with an acknowledge bit. Lastly, the master device transmits a stop condition to complete the single-byte data-write transfer.

Figure 40. Single Byte Write Transfer Timing

A multi-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted as shown in Figure 41. After receiving each data byte, the TAS5720L/M device responds with an acknowledge bit. Sequential data bytes are written to sequential addresses.

Figure 41. Multi-Byte Write Transfer Timing

7.3.2.2 Reading from the I²C Interface

As shown in Figure 41, a data-read transfer begins with the master device transmitting a start condition, followed by the I² device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal register to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5720L/M device address and the read/write bit, TAS5720L/M device responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5720L/M device address and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5720L/M device again responds with an acknowledge bit. Next, the TAS5720L/M device transmits the data byte from the register being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the data-read transfer.

Figure 42. Single Byte Read Transfer Timing

A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TAS5720L/M to the master device as shown Figure 43. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

Figure 43. Multi-Byte Read Transfer Timing

7.3.3 Serial Audio Interface (SAIF)

The TAS5720L/M device SAIF supports a variety of standard stereo serial audio formats including I²S, left-justifiedand Right Justified. The device also supports a time division multiplexed (TDM) format that is capable of transporting up to 8 channels of audio data on a single bus. LRCLK and SDIN are sampled on the rising edge of BCLK.

For the stereo formats (I²S, left-justified and right-justified), the TAS5720L/M device supports BCLK to LRCLK ratios of 32, 48 and 64. If the BCLK to LRCLK ratio is 64, MCLK can be tied directly to BCLK. Otherwise MCLK must be driven externally. The valid MCLK to LRCLK ratios are 64, 128, 256 and 512 as long as the frequency of MCLK is 25MHz or less.

For TDM operation, the TAS5720L/M device supports 4 or 8 channels for single speed (44.1/48 kHz) and double speed (88.2/96 kHz) sample rates. Each channel occupies a 32-bit time slot, therefore valid BCLK to LRCLK ratios are 128 and 256. MCLK can be tied to BCLK for all TDM modes or driven externally. If MCLK is driven externally, the MCLK to LRCLK ratio should be 64, 128, 256 or 512 and MCLK should be no faster than 25MHz.

The TAS5720L/M device selects the channel for playback based on either the I²C base address offset or based on a dedicated time slot selection register. See the Adjustable I2C Address section for more information.

7.3.3.1 Stereo I²S Format Timing

Figure 44 illustrates the timing of the stereo I²S format with 64 BCLKs per LRCLK. Two’s complement data is transmitted MSB to LSB with the left channel word beginning one BCLK after the falling edge of LRCLK and the right channel beginning one BCLK after the rising edge of LRCLK. Because data is MSB aligned to the beginning of word transmission, data precision does not be configured. Set the SAIF_FORMAT[2:0] register bits to I²S (register 0x02, bits 2:0=3’b100).

A. Data presented in two's-complement form with most significant bit (MSB) first.

Figure 44. I²S 64-f_SW Format

7.3.3.2 Stereo Left-Justified Format Timing

The stereo left justified format is very similar to the I²S format timing, except the data word begins transmission at the same cycle that LRCLK toggles (when it is shifted by one bit from I²S). The phase of LRCLK is also opposite of I²S. The left channel begins transmission when LRCLK transitions from low to high and the right channel begins transmission when LRCLK transitions from high-to-low. Set the SAIF_FORMAT[2:0] register bits to left-justified (register 0x02, bits 2:0=3’b101).The timing is illustrated in Figure 45.

A. Data presented in two's-complement form with most significant bit (MSB) first.

Figure 45. Left-Justified 64-f_SW Format

7.3.3.3 Stereo Right-Justified Format Timing

The stereo right justified format aligns the LSB of left channel data to the high to low transition of LRCLK and the LSB of the right channel data to the low to high transition of LRCLK. To insure data is received correctly, the SAIF must be configured for the proper data precision. The TAS5720L/M supports 16, 18, 20 and 24-bit data precision in right justified format. Set the SAIF_FORMAT[2:0] register bits (register 0x02, bits 2:0) to the appropriate right-justifiedsetting based on bit precision (value=3’b000 for 24-bit, 3’b001 for 20-bit, 3’b010 for 18-bit and 3’b011 for 16-bit). The timing is illustrated in Figure 46.

Figure 46. Right-Justified 64-f_SW Format

7.3.3.4 TDM Format Timing

A TDM frame begins with the low to high transition of LRCLK. As long as LRCLK is high for at least one BCLK period and low for one BCLK period, duty cycle is irrelevent. The SAIF automatically detects the number of time slots as long as valid BCLK to LRCLK ratios are utilized (see Serial Audio Interface (SAIF)).

For I²S aligned TDM operation (when time slot 0 begins one clock cycle after the low to high transition of LRCLK, set SAIF_FORMAT[2:0] register bits to I2S (register 0x02, bits 2:0=3’b100). Data is MSB aligned within the 32-bit time slots, therefore data precision is not required to be configured. The TDM format timing is illustrated in Figure 47.

Figure 47. TDM I²S Format

For left-justifiedTDM operation (when time slot 0 begins the cycle LRCLK transitions from low to high), SAIF_FORMAT[2:0] register bits to left-justified(register 0x02, bits 2:0=3’b101). As with I2S, data is MSB aligned. The timing is illustrated in Figure 48.

Figure 48. TDM Left- and Right-Justified Format

For right-justified TDM operation (when time slot 0 begins the cycle LRCLK transitions from low to high), data is LSB aligned to the 32-bit time slot. As with stereo right-justified formats, the TAS5720L/M must have the data precision configured. Set the SAIF_FORMAT[2:0] register bits (register 0x02, bits 2:0) to the appropriate right-justified setting based on bit precision (value=3’b000 for 24-bit, 3’b001 for 20-bit, 3’b010 for 18-bit and 3’b011 for 16-bit). The timing shown in Figure 48 is the same as left-justified TDM, with the data LSB aligned.

7.3.4 Audio Signal Path

Figure 49 illustrates the audio signal flow from the TDM SAIF to the speaker.

Figure 49. Audio Signal Path

7.3.4.2 Amplifier Analog Gain and Digital Volume Control

The gain from TDM SAIF to speaker is controlled by setting the amplifier’s analog gain and digital volume control. Amplifier analog gain settings are presented as the output level in dBV (dB relative to 1 Vrms) with a full scale serial audio input (0 dBFS) and the digital volume control set to 0 dB. These levels might not be achievable because of analog clipping in the amplifier, therefore they should be used to convey gain only.

Table 4 outlines each gain setting expressed in dBV and V_PK.

Table 4. Amplifier Gain Settings

ANALOG_GAIN {1:0} SETTING	FULL SCALE OUTPUT
	dBV	VPEAK
00	19.2	12.9
01	20.7	15.3
10	23.5	21.2
11	26.3	29.2

Equation 1 calculates the amplifiers output voltage.

Equation 1.

where

• V_AMP is the amplifier output voltage in dBV
• Input is the digital input amplitude in dB with respect to 0 dBFS
• A_DVC is the digital volume control setting, –100 dB to 24dB in 0.5-dB steps
• A_AMP is the amplifier analog gain setting (19.2, 20.7, 23.5, or 26.3) in dBV

Clipping in the digital domain occurs if the input level (in dB relative to 0 dBFS) plus the digital volume control setting (in dB) are greater than 0 dB. The signal path has approximately 0.5 dB of headroom, but TI does not recommend utilizing it.

The digital volume control can be adjusted from –100 dB to 24 dB in 0.5-dB steps. Equation 2 calculates the 8-bit volume control register setting at address 0x04.

Equation 2.

For example, digital volume settings of 0 dB, 24 dB and –100 dB map to 0xCF, 0xFF and 0x07 respectively. Values below 0x07 are equivalent to mute (the amplifier continues to switch with no audio).When a change in digital volume control occurs, the device ramps the volume to the new setting in 0.5 dB steps after every 8 audio samples to ensure smooth transitions in volume.

The Class-D amplifier uses a closed-loop architecture, therefore the gain does not depend on the supply input (V_PVDD). The approximate threshold for the onset of analog clipping is calculated in Equation 3.

Equation 3.

where

• V_{PK(max,preclip)} is the maximum peak unclipped output voltage in V
• V_PVDD is the power supply voltage
• R_L is the speaker load in Ω
• R_interconnect is the additional resistance in the PCB (such as cabling and filters) in Ω
• R_DS(on) is the power stage total on resistance (FET+bonding+packaging) in Ω

The effective on-resistance for this device (including FETs, bonding and packaging leads) is approximately 150 mΩ at room temperature and increasex by approximately 1.6 times over 100°C rise in temperature.Table 5 shows approximate maximum unclipped peak output voltages at room temperature (excluding interconnect resistances).

Table 5. Approximate Maximum Unclipped Peak Output Voltage at Room Temperature

SUPPLY VOLTAGE VPVDD (V)	MAXIMUM UNCLIPPED PEAK VOLTAGE VPK (V)
	RL = 4 Ω	RL = 8 Ω
12	11.16	11.57
17	15.81	16.39

7.3.4.3 Digital Clipper

The digital clipper hard limits the maximum DAC sample value, which provides a simple hardware mechanism to control the largest signal applied to the speaker. Because this block resides in the digital domain, the actual maximum output voltage also depends on the amplifier gain setting and the supply voltage (V_PVDD) limited amplifier voltage swing (For example, analog clipping can occur before digital clipping).

The maximum amplifier output voltage (excluding limitation due to swing) is calculated in Equation 4.

Equation 4.

where

• V_AMP(max,dc) is the amplifier maximum output voltage in dBV
• DC_level is the digital clipper level
• A_AMP is the amplifier analog gain setting (19.2, 20.7, 23.5, or 26.3) in dBV

Configure the digital clipper by writing the 20-bit DC_level to registers 0x01, 0x10 and 0x11. Set the DC_level to 0xFFFFF effectively bypasses the digital clipper.

Table 8. Typical Current Consumption⁽¹⁾

7.4.1 Shutdown Mode (SDZ)

The device enters shutdown mode if either the SDZ pin is asserted low or the I²C SDZ register bit is set low (bit 0, reg 0x01). In shutdown mode, the device consumes the minimum quiescent current with most analog and digital blocks powered down. The Class-D amplifier power stage powers down and the output pins are in a Hi-Z state. I²C communication remains possible in shutdown mode and register bits states are retained.

If a latching fault condition has occurred (over temperature, Over Current or DC detect), the SDZ pin or I²C bit must toggle low before the fault register can be cleared. For more information on faults and recovery, see the Faults and Status section.

When the device exits shutdown mode (by releasing both the SDZ pin high and setting the I²C SDZ register bit high), the device powers up the internal analog and digital blocks required for operation. If the I²C SLEEP bit is set low (bit 1, reg 0x01), the device powers up the Class-D amplifier and begins the switching of the power stage. If the I²C MUTE bit is set low (bit 4, reg 0x03), the device ramps up the volume to the current setting and begins playing audio.

If shutdown mode is asserted while audio is playing, the device ramps down the volume on the audio, stops the Class-D switching, puts the Class-D power stage output pins in a Hi-Z state and powers down the analog and digital blocks.

7.4.2 Sleep Mode

Sleep mode is similar to shutdown mode, except analog and digital blocks required to begin playing audio quickly are left powered up. Sleep mode operates as a hard mute where the Class-D amplifier stops switching, but the device does not power down completely. Entering sleep mode does not clear latching faults.

7.4.3 Active Mode

If shutdown mode and sleep mode are not asserted, the device is in active mode. During active mode, audio playback is enabled.

7.4.4 Mute Mode

When the I²C_MUTE bit is set high (bit 4, reg 0x03) and the device is in active mode, the volume is ramped down and the Class-D amplifier continues to operate with an idle audio input.

7.4.5 Faults and Status

During the power-up sequence, the power-on-reset circuit (POR) monitoring the DVDD pin domain releases all registers from reset (including the I²C registers) once DVDD is valid. The device does not exit shutdown mode until the PVDD pin has a valid voltage between the undervoltage lockout (UVLO) and overvoltage lockout (OVLO) thresholds. If DVDD drops below the POR threshold the device transitions into shutdown mode with all registers held in reset. If UVLO or OVLO thresholds are violated by the PVDD pin thresholds, the device transitions into shutdown mode, but registers are not be forced into reset. Both of the conditions are non-latching and the device operates normally once supply voltages are valid again. The device can be reset only by reducing DVDD below the POR threshold.

The device transitions into sleep mode if it detects any faults with the SAIF clocks such as

• Invalid MCLK to LRCLK and BCLK to LRCLK ratios
• Invalid MCLK and LRCLK switching rates
• Halting of MCLK, BCLK or LRCLK switching

Upon detection of a SAIF clock error, the device transitions into sleep mode as quickly as possible to limit the possibility of audio artifacts. Once all SAIF clock errors are resolved, the device will volume ramp back to the previous playback state. During a SAIF clock error, the FAULTZ pin will be asserted low and the CLKE bit will be asserted high (register 0x08, bit 3).

While operating in shutdown mode, the SAIF clock error detect circuitry powers down and the CLKE bit reads high. This reading is not an indication of a SAIF clock error. If the device has not entered active mode after a power-up sequence or after transitioning out of shutdown mode, the FAULTZ pin pulses low for only approximately 10 µs every 350 µs. This action prevents a possible locking condition if the FAULTZ is connected to the SDZ pin to accomplish automatic recovery. Once the device has entered active mode one time (after power up or deassertion of shutdown mode), the SAIF clock errors pull the FAULTZ pin low continuously until the fault has cleared.

The device also monitors die temperature, power stage load current and amplifier output DC content and issues latching faults if any of the conditions occur. A die temperature of approximately 150°C causes the device to enter sleep mode and issue an Over-temperature error (OTE) readable via I²C (bit 0, reg 0x08).

Sustained excessive DC content at the output of the Class-D amplifier can damage loudspeakers via voice coil heating. The amplifier has an internal circuit to detect significant DC content that forces the device into sleep mode. The device issues a DC detect error (DCE) readable via I²C (bit 1, reg 0x08).

If the Class-D amplifier load current exceeds the threshold set by the OC_THRESH register bits (bits 5-4, reg 0x08), the device enters sleep mode and issues an Over Current Error (OCE) that is readable via I²C (bit 2, reg 0x08).

During OTE, DCE and OCE, the FAULTZ pin asserts low until the latched fault is cleared. FAULTZ is an open drain pin and requires a pull-up resistor to the DVDD pin.

Latched faults can be cleared only by toggling the SDZ pin or SDZ I²C bit (bit 0, reg 0x01). This toggle does not clear I²C registers (except the fault status of OTE, OCE and DCE). If the device is intended to attempt automatic recovery after latching faults, implement a circuit like the one shown in Figure 50. The device waits approximately 650 ms after a DCE fault has cleared and 1.3 s after an OTE or OCE fault has cleared before releasing FAULTZ high and allowing the device to enter active mode.

Figure 50. Auto Recovery Circuit

Table 9. I²C Register Map Summary

7.5.1 Device Identification

7.5.2 Power Control Register

7.5.3 Digital Control Register 1

7.5.4 Digital Control Register 2

7.5.5 Volume Control Register

7.5.6 Analog Control Register

7.5.7 Fault Configuration and Error Status Register

7.5.8 Digital Clipper 2

7.5.9 Digital Clipper 1