SLOS982C August   2017  – April 2018 TAS5755M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Efficiency vs Total Output Power
      2.      Output Power vs Supply Voltage
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  PWM Operation at Recommended Operating Conditions
    6. 7.6  DC Electrical Characteristics
    7. 7.7  AC Electrical Characteristics (BTL, PBTL)
    8. 7.8  Electrical Characteristics - PLL External Filter Components
    9. 7.9  Electrical Characteristic - I2C Serial Control Port Operation
    10. 7.10 Timing Requirements - PLL Input Parameters
    11. 7.11 Timing Requirements - Serial Audio Ports Slave Mode
    12. 7.12 Timing Requirements - I2C Serial Control Port Operation
    13. 7.13 Timing Requirements - Reset (RESET)
    14. 7.14 Typical Characteristics
      1. 7.14.1 Typical Characteristics, 2.1 SE Configuration
      2. 7.14.2 Typical Characteristics, 2.0 BTL Configuration
      3. 7.14.3 Typical Characteristics, PBTL Configuration
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  Power Supply
      2. 9.3.2  I2C Address Selection and Fault Output
      3. 9.3.3  Single-Filter PBTL Mode
      4. 9.3.4  Device Protection System
        1. 9.3.4.1 Overcurrent (OC) Protection With Current Limiting
        2. 9.3.4.2 Overtemperature Protection
        3. 9.3.4.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
      5. 9.3.5  SSTIMER Functionality
      6. 9.3.6  Clock, Autodetection, and PLL
      7. 9.3.7  PWM Section
      8. 9.3.8  2.1-Mode Support
      9. 9.3.9  I2C Compatible Serial Control Interface
      10. 9.3.10 Audio Serial Interface
        1. 9.3.10.1 I2S Timing
        2. 9.3.10.2 Left-Justified
        3. 9.3.10.3 Right-Justified
      11. 9.3.11 Dynamic Range Control (DRC)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Stereo BTL Mode
      2. 9.4.2 Mono PBTL Mode
      3. 9.4.3 2.1 Mode
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Control Interface
        1. 9.5.1.1 General I2C Operation
        2. 9.5.1.2 Single- and Multiple-Byte Transfers
        3. 9.5.1.3 Single-Byte Write
        4. 9.5.1.4 Multiple-Byte Write
        5. 9.5.1.5 Single-Byte Read
        6. 9.5.1.6 Multiple-Byte Read
      2. 9.5.2 26-Bit 3.23 Number Format
    6. 9.6 Register Maps
      1. 9.6.1 Register Map Summary
      2. 9.6.2 Register Maps
        1. 9.6.2.1  Clock Control Register (0x00)
        2. 9.6.2.2  Device ID Register (0x01)
        3. 9.6.2.3  Error Status Register (0x02)
        4. 9.6.2.4  System Control Register 1 (0x03)
        5. 9.6.2.5  Serial Data Interface Register (0x04)
        6. 9.6.2.6  System Control Register 2 (0x05)
        7. 9.6.2.7  Soft Mute Register (0x06)
        8. 9.6.2.8  Volume Registers (0x07, 0x08, 0x09, 0x0A)
        9. 9.6.2.9  Volume Configuration Register (0x0E)
        10. 9.6.2.10 Modulation Limit Register (0x10)
        11. 9.6.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
        12. 9.6.2.12 PWM Shutdown Group Register (0x19)
        13. 9.6.2.13 Start/Stop Period Register (0x1A)
        14. 9.6.2.14 Oscillator Trim Register (0x1B)
        15. 9.6.2.15 BKND_ERR Register (0x1C)
        16. 9.6.2.16 Input Multiplexer Register (0x20)
        17. 9.6.2.17 Channel 4 Source Select Register (0x21)
        18. 9.6.2.18 PWM Output Mux Register (0x25)
        19. 9.6.2.19 DRC Control Register (0x46)
        20. 9.6.2.20 Bank Switch and EQ Control Register (0x50)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo Bridge Tied Load Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Component Selection and Hardware Connections
          2. 10.2.1.2.2 I2C Pullup Resistors
          3. 10.2.1.2.3 Digital I/O Connectivity
          4. 10.2.1.2.4 Recommended Start-Up and Shutdown Procedures
            1. 10.2.1.2.4.1 Initialization Sequence
            2. 10.2.1.2.4.2 Normal Operation
            3. 10.2.1.2.4.3 Shutdown Sequence
            4. 10.2.1.2.4.4 Power-Down Sequence
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Mono Parallel Bridge Tied Load Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 2.1 Application
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 DVDD and AVDD Supplies
    2. 11.2 PVDD Power Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TAS5755M is a single-chip flexible digital audio solution with integrated processing that supports 2.1 (2 speakers + subwoofer), 2.0 or stereo (2 speakers) and mono (high power speaker) modes.

Its high efficiency, low 80 mΩ RDSON and pad-up package allows the device to output up to 2 × 50 W or 1 × 100 W.

TAS5755M leverages 2 full H-bridges which are used for each channel in stereo mode. In 2.1 mode, TAS5755M runs 2 independent speaker channels using 2 half-bridges while using a full-bridge to drive a subwoofer. Finally, in mono mode, TAS5755M supports pre-filter parallel bridge tied load (PBTL) using only one filter stage to reduce total system size and cost.

TAS5755M has integrated audio processing. It includes: signal mixing, DC blocking filters, 2 × 8 + 1 × 2 biquads for equalization. Power limiting is implemented by leveraging a two-band log-style DRC and a separate single-band DRC for the subwoofer channel.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TAS5755M DFD 14 mm × 6.1 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.