SLOS782C July   2013  – May  2017 TAS5760L

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Digital I/O Pins
    6. 7.6  Master Clock
    7. 7.7  Serial Audio Port
    8. 7.8  Protection Circuitry
    9. 7.9  Speaker Amplifier in All Modes
    10. 7.10 Speaker Amplifier in Stereo Bridge-Tied Load (BTL) Mode
    11. 7.11 Speaker Amplifier in Mono Parallel Bridge-Tied Load (PBTL) Mode
    12. 7.12 I²C Control Port
    13. 7.13 Typical Idle, Mute, Shutdown, Operational Power Consumption
    14. 7.14 Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode)
    15. 7.15 Typical Performance Characteristics (Mono PBTL Mode)
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Speaker Amplifier Audio Signal Path
        1. 9.3.2.1 Serial Audio Port (SAP)
          1. 9.3.2.1.1 I²S Timing
          2. 9.3.2.1.2 Left-Justified
          3. 9.3.2.1.3 Right-Justified
        2. 9.3.2.2 DC Blocking Filter
        3. 9.3.2.3 Digital Boost and Volume Control
        4. 9.3.2.4 Digital Clipper
        5. 9.3.2.5 Closed-Loop Class-D Amplifier
      3. 9.3.3 Speaker Amplifier Protection Suite
        1. 9.3.3.1 Speaker Amplifier Fault Notification (SPK_FAULT Pin)
        2. 9.3.3.2 DC Detect Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Hardware Control Mode
        1. 9.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 9.4.1.2 Serial Audio Port in Hardware Control Mode
        3. 9.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
        4. 9.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
        5. 9.4.1.5 Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)
        6. 9.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
        7. 9.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
        8. 9.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure
          1. 9.4.1.8.1 Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
      2. 9.4.2 Software Control Mode
        1. 9.4.2.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 9.4.2.2 Serial Audio Port Controls
          1. 9.4.2.2.1 Serial Audio Port (SAP) Clocking
        3. 9.4.2.3 Parallel Bridge Tied Load Mode via Software Control
        4. 9.4.2.4 Speaker Amplifier Gain Structure
          1. 9.4.2.4.1 Speaker Amplifier Gain in Software Control Mode
          2. 9.4.2.4.2 Considerations for Setting the Speaker Amplifier Gain Structure
          3. 9.4.2.4.3 Recommendations for Setting the Speaker Amplifier Gain Structure in Software Control Mode
        5. 9.4.2.5 I²C Software Control Port
          1. 9.4.2.5.1 Setting the I²C Device Address
          2. 9.4.2.5.2 General Operation of the I²C Control Port
          3. 9.4.2.5.3 Writing to the I²C Control Port
          4. 9.4.2.5.4 Reading from the I²C Control Port
    5. 9.5 Register Maps
      1. 9.5.1 Control Port Registers - Quick Reference
      2. 9.5.2 Control Port Registers - Detailed Description
        1. 9.5.2.1  Device Identification Register (0x00)
        2. 9.5.2.2  Power Control Register (0x01)
        3. 9.5.2.3  Digital Control Register (0x02)
        4. 9.5.2.4  Volume Control Configuration Register (0x03)
        5. 9.5.2.5  Left Channel Volume Control Register (0x04)
        6. 9.5.2.6  Right Channel Volume Control Register (0x05)
        7. 9.5.2.7  Analog Control Register (0x06)
        8. 9.5.2.8  Reserved Register (0x07)
        9. 9.5.2.9  Fault Configuration and Error Status Register (0x08)
        10. 9.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F)
        11. 9.5.2.11 Digital Clipper Control 2 Register (0x10)
        12. 9.5.2.12 Digital Clipper Control 1 Register (0x11)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Using Software Control
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Startup Procedures- Software Control Mode
          2. 10.2.1.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.1.2.3 Component Selection and Hardware Connections
            1. 10.2.1.2.3.1 I²C Pullup Resistors
            2. 10.2.1.2.3.2 Digital I/O Connectivity
          4. 10.2.1.2.4 Recommended Startup and Shutdown Procedures
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Stereo BTL Using Hardware Control
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.2.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.2.2.3 Digital I/O Connectivity
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Mono PBTL Using Software Control
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
          1. 10.2.3.2.1 Startup Procedures- Software Control Mode
          2. 10.2.3.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.3.2.3 Component Selection and Hardware Connections
            1. 10.2.3.2.3.1 I²C Pull-Up Resistors
            2. 10.2.3.2.3.2 Digital I/O Connectivity
        3. 10.2.3.3 Application Curve
      4. 10.2.4 Mono PBTL Using Hardware Control
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
          1. 10.2.4.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.4.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.4.2.3 Component Selection and Hardware Connections
          4. 10.2.4.2.4 Digital I/O Connectivity
        3. 10.2.4.3 Application Curve
      5. 10.2.5 Stereo BTL Using Software Control, 32-Pin DAP Package Option
        1. 10.2.5.1 Design Requirements
        2. 10.2.5.2 Detailed Design Procedure
          1. 10.2.5.2.1 Startup Procedures- Software Control Mode
          2. 10.2.5.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.5.2.3 Component Selection and Hardware Connections
            1. 10.2.5.2.3.1 I²C Pullup Resistors
            2. 10.2.5.2.3.2 Digital I/O Connectivity
          4. 10.2.5.2.4 Recommended Startup and Shutdown Procedures
        3. 10.2.5.3 Application Curve
      6. 10.2.6 Stereo BTL Using Hardware Control, 32-Pin DAP Package Option
        1. 10.2.6.1 Design Requirements
        2. 10.2.6.2 Detailed Design Procedure
          1. 10.2.6.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.6.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.6.2.3 Digital I/O Connectivity
        3. 10.2.6.3 Application Curve
      7. 10.2.7 Mono PBTL Using Software Control, 32-Pin DAP Package Option
        1. 10.2.7.1 Design Requirements
        2. 10.2.7.2 Detailed Design Procedure
          1. 10.2.7.2.1 Startup Procedures- Software Control Mode
          2. 10.2.7.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.7.2.3 Component Selection and Hardware Connections
            1. 10.2.7.2.3.1 I²C Pull-Up Resistors
            2. 10.2.7.2.3.2 Digital I/O Connectivity
        3. 10.2.7.3 Application Curve
      8. 10.2.8 Mono PBTL Using Hardware Control, 32-Pin DAP Package Option
        1. 10.2.8.1 Design Requirements
        2. 10.2.8.2 Detailed Design Procedure
          1. 10.2.8.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.8.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.8.2.3 Component Selection and Hardware Connections
          4. 10.2.8.2.4 Digital I/O Connectivity
        3. 10.2.8.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 DVDD Supply
    2. 11.2 PVDD Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General Guidelines for Audio Amplifiers
      2. 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 12.1.3 Optimizing Thermal Performance
        1. 12.1.3.1 Device, Copper, and Component Layout
        2. 12.1.3.2 Stencil Pattern
          1. 12.1.3.2.1 PCB Footprint and Via Arrangement
            1. 12.1.3.2.1.1 Solder Stencil
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

These typical connection diagrams highlight the required external components and system level connections for proper operation of the device in several popular use cases.

Each of these configurations can be realized using the Evaluation Modules (EVMs) for the device. These flexible modules allow full evaluation of the device in all available modes of operation. Additionally, some of the application circuits are available as reference designs and can be found on the TI website. Also see the TAS5760L's product page for information on ordering the EVM. Not all configurations are available as reference designs; however, any design variation can be supported by TI through schematic and layout reviews. Visit support.ti.com for additional design assistance. Also, join the audio amplifier discussion forum at http://e2e.ti.com.

10.2 Typical Applications

These application circuits detail the recommended component selection and board configurations for the TAS5760L device. Note that in Software Control mode, the clipping point of the amplifier and thus the rated power of the end equipment can be set using the digital clipper if desired. Additionally, if the sonic signature of the soft clipper is preferred, it can be used in addition to or in lieu of the digital clipper. The software control application circuit detailed in this section shows the soft clipper in its bypassed state, which results in a lower BOM count than when using the soft clipper. The trade-off between the sonic characteristics of the clipping events in the amplifier and BOM minimization can be chosen based upon the design goals related to the end product.

10.2.1 Stereo BTL Using Software Control

TAS5760L stereo_btl_sw_ctrl.gif Figure 57. Stereo BTL Using Software Control

10.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 19 as the input parameters.

Table 19. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 5 V to 15 V
Host Processor I2S Compliant Master
I2C Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speakers 4 Ω to 8 Ω

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Startup Procedures- Software Control Mode

  1. Configure all digital I/O pins as required by the application using PCB connections (that is SPK_GAIN[1:0] = 11, ADR, etc.)
  2. Start with SPK_SD Pin = LOW
  3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
  4. Once power supplies are stable, start MCLK, SCLK, LRCK
  5. Configure the device via the control port in the manner required by the use case, making sure to mute the device via the control port
  6. Once power supplies and clocks are stable and the control port has been programmed, bring SPK_SD HIGH
  7. Unmute the device via the control port
  8. The device is now in normal operation

NOTE

Control port register changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.

10.2.1.2.2 Shutdown Procedures- Software Control Mode

  1. The device is in normal operation
  2. Mute via the control port
  3. Pull SPK_SD LOW
  4. The clocks can now be stopped and the power supplies brought down
  5. The device is now fully shutdown and powered off

NOTE

Any control port register changes excluding volume control changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.

10.2.1.2.3 Component Selection and Hardware Connections

details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.

10.2.1.2.3.1 I²C Pullup Resistors

It is important to note that when the device is operated in Software Control Mode, the customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, because they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification.

10.2.1.2.3.2 Digital I/O Connectivity

The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

10.2.1.2.4 Recommended Startup and Shutdown Procedures

The start up and shutdown procedures for both Hardware Control Mode and Software Control Mode are shown below.

10.2.1.3 Application Curve

Table 20. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 1. Output Power vs PVDD G001
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G024
Figure 5. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G027
Figure 7. Efficiency vs Output Power G030
Figure 8. Crosstalk vs Frequency G031
Figure 9. PVDD PSRR vs Frequency G019
Figure 10. DVDD PSRR vs Frequency G020
Figure 11. Idle Current Draw vs PVDD (Filterless) G042
Figure 12. Idle Current Draw vs PVDD (With LC Filter as Shown on the EVM) G023
Figure 13. Shutdown Current Draw vs PVDD (Filterless) G022
Figure 14. Output Power vs PVDD G039
Figure 15. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G002
Figure 18. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G008
Figure 20. Efficiency vs Output Power G014
Figure 21. Crosstalk vs Frequency G018
Figure 22. PVDD PSRR vs Frequency G019
Figure 23. Idle Current Draw vs PVDD (Filterless) G045
Figure 24. Idle Current Draw vs PVDD (With LC Filter as Shown on EVM) G044
Figure 25. Shutdown Current Draw vs PVDD (Filterless) G022

10.2.2 Stereo BTL Using Hardware Control

TAS5760L stereo_btl_hw_ctrl.gif Figure 58. Stereo BTL Using Hardware Control

10.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 21 as the input parameters.

Table 21. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 5 V to 15 V
Host Processor I2S Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speakers 4 Ω to 8 Ω

10.2.2.2 Detailed Design Procedure

10.2.2.2.1 Startup Procedures- Hardware Control Mode

  1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ, GAIN, etc.)
  2. Start with SPK_SD pin pulled LOW and SPK_SLEEP/ADR pin pulled HIGH
  3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
  4. Once power supplies are stable, start MCLK, SCLK, LRCK
  5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring SPK_SD HIGH
  6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR LOW
  7. The device is now in normal operation

10.2.2.2.2 Shutdown Procedures- Hardware Control Mode

  1. The device is in normal operation
  2. Pull SPK_SLEEP/ADR HIGH
  3. Pull SPK_SD LOW
  4. The clocks can now be stopped and the power supplies brought down
  5. The device is now fully shutdown and powered off

10.2.2.2.3 Digital I/O Connectivity

The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

10.2.2.3 Application Curve

Table 22. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 1. Output Power vs PVDD G001
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G024
Figure 4. Idle Channel Noise vs PVDD G026
Figure 5. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G027
Figure 7. Efficiency vs Output Power G030
Figure 8. Crosstalk vs Frequency G031
Figure 9. PVDD PSRR vs Frequency G019
Figure 10. DVDD PSRR vs Frequency G020
Figure 11. Idle Current Draw vs PVDD (Filterless) G042
Figure 12. Idle Current Draw vs PVDD (With LC Filter as Shown on the EVM) G023
Figure 13. Shutdown Current Draw vs PVDD (Filterless) G022
Figure 14. Output Power vs PVDD G039
Figure 15. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G002
Figure 17. Idle Channel Noise vs PVDD G006
Figure 18. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G008
Figure 20. Efficiency vs Output Power G014
Figure 21. Crosstalk vs Frequency G018
Figure 22. PVDD PSRR vs Frequency G019
Figure 23. Idle Current Draw vs PVDD (Filterless) G045
Figure 24. Idle Current Draw vs PVDD (With LC Filter as Shown on EVM) G044
Figure 25. Shutdown Current Draw vs PVDD (Filterless) G022

10.2.3 Mono PBTL Using Software Control

TAS5760L mono_pbtl_sw_ctrl2.gif Figure 59. Mono PBTL Using Software Control

10.2.3.1 Design Requirements

For this design example, use the parameters listed in Table 23 as the input parameters.

Table 23. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 5 V to 15 V
Host Processor I2S Compliant Master
I2C Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speakers 4 Ω to 8 Ω

10.2.3.2 Detailed Design Procedure

10.2.3.2.1 Startup Procedures- Software Control Mode

  1. Configure all digital I/O pins as required by the application using PCB connections (that is SPK_GAIN[1:0] = 11, ADR, etc.)
  2. Start with SPK_SD Pin = LOW
  3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
  4. Once power supplies are stable, start MCLK, SCLK, LRCK
  5. Configure the device via the control port in the manner required by the use case, making sure to mute the device via the control port
  6. Once power supplies and clocks are stable and the control port has been programmed, bring SPK_SD HIGH
  7. Unmute the device via the control port
  8. The device is now in normal operation

NOTE

Control port register changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.

10.2.3.2.2 Shutdown Procedures- Software Control Mode

  1. The device is in normal operation
  2. Mute via the control port
  3. Pull SPK_SD LOW
  4. The clocks can now be stopped and the power supplies brought down
  5. The device is now fully shutdown and powered off

NOTE

Any control port register changes excluding volume control changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.

10.2.3.2.3 Component Selection and Hardware Connections

above details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.

10.2.3.2.3.1 I²C Pull-Up Resistors

It is important to note that when the device is operated in Software Control Mode, the customary pull-up resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, since they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification.

10.2.3.2.3.2 Digital I/O Connectivity

The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

10.2.3.3 Application Curve

Table 24. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 27. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G032
Figure 29. THD+N vs Output Power With PVDD = 12 V With 1 kHz Sine Input G035
Figure 37. Efficiency vs Output Power G038
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G004
Figure 35. THD+N vs Output Power With PVDD = 12 V G011
Figure 7. Efficiency vs Output Power G015

10.2.4 Mono PBTL Using Hardware Control

TAS5760L mono_pbtl_hw_ctrl.gif Figure 60. Mono PBTL Using Hardware Control

10.2.4.1 Design Requirements

For this design example, use the parameters listed in Table 25 as the input parameters.

Table 25. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 5 V to 15 V
Host Processor I2S Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speakers 4 Ω to 8 Ω

10.2.4.2 Detailed Design Procedure

10.2.4.2.1 Startup Procedures- Hardware Control Mode

  1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ, GAIN, etc.)
  2. Start with SPK_SD pin pulled LOW and SPK_SLEEP/ADR pin pulled HIGH
  3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
  4. Once power supplies are stable, start MCLK, SCLK, LRCK
  5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring SPK_SD HIGH
  6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR LOW
  7. The device is now in normal operation

10.2.4.2.2 Shutdown Procedures- Hardware Control Mode

  1. The device is in normal operation
  2. Pull SPK_SLEEP/ADR HIGH
  3. Pull SPK_SD LOW
  4. The clocks can now be stopped and the power supplies brought down
  5. The device is now fully shutdown and powered off

10.2.4.2.3 Component Selection and Hardware Connections

details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.

10.2.4.2.4 Digital I/O Connectivity

The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

10.2.4.3 Application Curve

Table 26. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 32. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G032
Figure 34. Idle Channel Noise vs PVDD G034
Figure 29. THD+N vs Output Power With PVDD = 12 V With 1 kHz Sine Input G035
Figure 37. Efficiency vs Output Power G038
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G004
Figure 17. Idle Channel Noise vs PVDD G007
Figure 35. THD+N vs Output Power With PVDD = 12 V G011
Figure 7. Efficiency vs Output Power G015

10.2.5 Stereo BTL Using Software Control, 32-Pin DAP Package Option

TAS5760L TAC_32P_BTL_SW.gif Figure 61. Stereo BTL using Software Control, 32-Pin DAP Package Option

10.2.5.1 Design Requirements

For this design example, use the parameters listed in Table 27 as the input parameters.

Table 27. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 5 V to 15 V
Host Processor I2S Compliant Master
I2C Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speakers 4 Ω to 8 Ω

10.2.5.2 Detailed Design Procedure

10.2.5.2.1 Startup Procedures- Software Control Mode

  1. Configure all digital I/O pins as required by the application using PCB connections (that is SPK_GAIN[1:0] = 11, ADR, etc.)
  2. Start with SPK_SD Pin = LOW
  3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
  4. Once power supplies are stable, start MCLK, SCLK, LRCK
  5. Configure the device via the control port in the manner required by the use case, making sure to mute the device via the control port
  6. Once power supplies and clocks are stable and the control port has been programmed, bring SPK_SD HIGH
  7. Unmute the device via the control port
  8. The device is now in normal operation

NOTE

Control port register changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.

10.2.5.2.2 Shutdown Procedures- Software Control Mode

  1. The device is in normal operation
  2. Mute via the control port
  3. Pull SPK_SD LOW
  4. The clocks can now be stopped and the power supplies brought down
  5. The device is now fully shutdown and powered off

NOTE

Any control port register changes excluding volume control changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.

10.2.5.2.3 Component Selection and Hardware Connections

Figure 61 details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.

10.2.5.2.3.1 I²C Pullup Resistors

It is important to note that when the device is operated in Software Control Mode, the customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, because they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification.

10.2.5.2.3.2 Digital I/O Connectivity

The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

10.2.5.2.4 Recommended Startup and Shutdown Procedures

The start up and shutdown procedures for both Hardware Control Mode and Software Control Mode are shown below.

10.2.5.3 Application Curve

Table 28. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 1. Output Power vs PVDD G001
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G024
Figure 5. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G027
Figure 7. Efficiency vs Output Power G030
Figure 8. Crosstalk vs Frequency G031
Figure 22. PVDD PSRR vs Frequency G019
Figure 10. DVDD PSRR vs Frequency G020
Figure 11. Idle Current Draw vs PVDD (Filterless) G042
Figure 12. Idle Current Draw vs PVDD (With LC Filter as Shown on the EVM) G023
Figure 13. Shutdown Current Draw vs PVDD (Filterless) G022
Figure 14. Output Power vs PVDD G039
Figure 15. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G002
Figure 18. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G008
Figure 7. Efficiency vs Output Power G014
Figure 21. Crosstalk vs Frequency G018
Figure 22. PVDD PSRR vs Frequency G019
Figure 23. Idle Current Draw vs PVDD (Filterless) G045
Figure 24. Idle Current Draw vs PVDD (With LC Filter as Shown on EVM) G044
Figure 25. Shutdown Current Draw vs PVDD (Filterless) G022

10.2.6 Stereo BTL Using Hardware Control, 32-Pin DAP Package Option

TAS5760L TAC_32P_BTL_HW.gif Figure 62. Stereo BTL using Hardware Control, 32-Pin DAP Package Option

10.2.6.1 Design Requirements

For this design example, use the parameters listed in Table 29 as the input parameters.

Table 29. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 5 V to 15 V
Host Processor I2S Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speakers 4 Ω to 8 Ω

10.2.6.2 Detailed Design Procedure

10.2.6.2.1 Startup Procedures- Hardware Control Mode

  1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ, GAIN, etc.)
  2. Start with SPK_SD pin pulled LOW and SPK_SLEEP/ADR pin pulled HIGH
  3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
  4. Once power supplies are stable, start MCLK, SCLK, LRCK
  5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring SPK_SD HIGH
  6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR LOW
  7. The device is now in normal operation

10.2.6.2.2 Shutdown Procedures- Hardware Control Mode

  1. The device is in normal operation
  2. Pull SPK_SLEEP/ADR HIGH
  3. Pull SPK_SD LOW
  4. The clocks can now be stopped and the power supplies brought down
  5. The device is now fully shutdown and powered off

10.2.6.2.3 Digital I/O Connectivity

The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

10.2.6.3 Application Curve

Table 30. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 1. Output Power vs PVDD G001
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G024
Figure 4. Idle Channel Noise vs PVDD G026
Figure 5. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G027
Figure 7. Efficiency vs Output Power G030
Figure 8. Crosstalk vs Frequency G031
Figure 22. PVDD PSRR vs Frequency G019
Figure 10. DVDD PSRR vs Frequency G020
Figure 11. Idle Current Draw vs PVDD (Filterless) G042
Figure 12. Idle Current Draw vs PVDD (With LC Filter as Shown on the EVM) G023
Figure 13. Shutdown Current Draw vs PVDD (Filterless) G022
Figure 14. Output Power vs PVDD G039
Figure 15. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G002
Figure 17. Idle Channel Noise vs PVDD G006
Figure 18. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G008
Figure 7. Efficiency vs Output Power G014
Figure 21. Crosstalk vs Frequency G018
Figure 22. PVDD PSRR vs Frequency G019
Figure 23. Idle Current Draw vs PVDD (Filterless) G045
Figure 24. Idle Current Draw vs PVDD (With LC Filter as Shown on EVM) G044
Figure 25. Shutdown Current Draw vs PVDD (Filterless) G022

10.2.7 Mono PBTL Using Software Control, 32-Pin DAP Package Option

TAS5760L TAC_32P_PBTL_SW.gif Figure 63. Mono PBTL using Software Control, 32-Pin DAP Package Option

10.2.7.1 Design Requirements

For this design example, use the parameters listed in Table 31 as the input parameters.

Table 31. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 5 V to 15 V
Host Processor I2S Compliant Master
I2C Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speakers 4 Ω to 8 Ω

10.2.7.2 Detailed Design Procedure

10.2.7.2.1 Startup Procedures- Software Control Mode

  1. Configure all digital I/O pins as required by the application using PCB connections (that is SPK_GAIN[1:0] = 11, ADR, etc.)
  2. Start with SPK_SD Pin = LOW
  3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
  4. Once power supplies are stable, start MCLK, SCLK, LRCK
  5. Configure the device via the control port in the manner required by the use case, making sure to mute the device via the control port
  6. Once power supplies and clocks are stable and the control port has been programmed, bring SPK_SD HIGH
  7. Unmute the device via the control port
  8. The device is now in normal operation

NOTE

Control port register changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.

10.2.7.2.2 Shutdown Procedures- Software Control Mode

  1. The device is in normal operation
  2. Mute via the control port
  3. Pull SPK_SD LOW
  4. The clocks can now be stopped and the power supplies brought down
  5. The device is now fully shutdown and powered off

NOTE

Any control port register changes excluding volume control changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.

10.2.7.2.3 Component Selection and Hardware Connections

Figure 63 above details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.

10.2.7.2.3.1 I²C Pull-Up Resistors

It is important to note that when the device is operated in Software Control Mode, the customary pull-up resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, since they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification.

10.2.7.2.3.2 Digital I/O Connectivity

The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

10.2.7.3 Application Curve

Table 32. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G032
Figure 29. THD+N vs Output Power With PVDD = 12 V With 1 kHz Sine Input G035
Figure 7. Efficiency vs Output Power G038
Figure 16. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G004
Figure 35. THD+N vs Output Power With PVDD = 12 V G011
Figure 31. Efficiency vs Output Power G015

10.2.8 Mono PBTL Using Hardware Control, 32-Pin DAP Package Option

TAS5760L TAC_32P_PBTL_HW.gif Figure 64. Mono PBTL using Hardware Control, 32 Pin DAP Package Option

10.2.8.1 Design Requirements

For this design example, use the parameters listed in Table 33 as the input parameters.

Table 33. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 5 V to 15 V
Host Processor I2S Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speakers 4 Ω to 8 Ω

10.2.8.2 Detailed Design Procedure

10.2.8.2.1 Startup Procedures- Hardware Control Mode

  1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ, GAIN, etc.)
  2. Start with SPK_SD pin pulled LOW and SPK_SLEEP/ADR pin pulled HIGH
  3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
  4. Once power supplies are stable, start MCLK, SCLK, LRCK
  5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring SPK_SD HIGH
  6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR LOW
  7. The device is now in normal operation

10.2.8.2.2 Shutdown Procedures- Hardware Control Mode

  1. The device is in normal operation
  2. Pull SPK_SLEEP/ADR HIGH
  3. Pull SPK_SD LOW
  4. The clocks can now be stopped and the power supplies brought down
  5. The device is now fully shutdown and powered off

10.2.8.2.3 Component Selection and Hardware Connections

Figure 64 details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.

10.2.8.2.4 Digital I/O Connectivity

The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

10.2.8.3 Application Curve

Table 34. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G032
Figure 34. Idle Channel Noise vs PVDD G034
Figure 29. THD+N vs Output Power With PVDD = 12 V With 1 kHz Sine Input G035
Figure 7. Efficiency vs Output Power G038
Figure 16. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G004
Figure 17. Idle Channel Noise vs PVDD G007
Figure 35. THD+N vs Output Power With PVDD = 12 V G011
Figure 31. Efficiency vs Output Power G015