9.6.1.23 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]
BQ_WR_CTRL1 is shown in Figure 104 and described in Table 29.
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Figure 104. BQ_WR_CTRL1 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
BQ_WR_FIRST_COEF |
R/W |
R/W |
|
Table 29. BQ_WR_CTRL1 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-1 |
RESERVED |
R/W |
0000000 |
This bit is reserved
|
0 |
BQ_WR_FIRST_COEF |
R/W |
0 |
Indicate the first coefficient of a BQ is starting to write.
|