SLASEO2 May   2019 TAS5806MD

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
      1. 7.7.1 Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode
      2. 7.7.2 Bridge Tied Load (BTL) Configuration Curves
      3. 7.7.3 Parallel Bridge Tied Load (PBTL) Configuration
      4. 7.7.4 Headphone Driver
      5. 7.7.5 Line Driver
  8. 8 Parametric Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Device Clocking
      3. 9.3.3 Serial Audio Port – Clock Rates
      4. 9.3.4 Clock Halt Auto-recovery
      5. 9.3.5 Sample Rate on the Fly Change
      6. 9.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 9.3.7 Digital Audio Processing
      8. 9.3.8 Class D Audio Amplifier
        1. 9.3.8.1 Speaker Amplifier Gain Select
    4. 9.4 Device Functional Modes
      1. 9.4.1 Software Control
      2. 9.4.2 Speaker Amplifier Operating Modes
        1. 9.4.2.1 BTL Mode
        2. 9.4.2.2 PBTL Mode
      3. 9.4.3 Low EMI Modes
        1. 9.4.3.1 Minimize EMI with Spread Spectrum
        2. 9.4.3.2 Channel to Channel Phase shift
        3. 9.4.3.3 Multi-Devices PWM Phase Synchronization
      4. 9.4.4 Thermal Foldback
      5. 9.4.5 Headphone Control
      6. 9.4.6 Device State Control
      7. 9.4.7 Device Modulation
        1. 9.4.7.1 BD Modulation
        2. 9.4.7.2 1SPW Modulation
        3. 9.4.7.3 Hybrid Modulation
    5. 9.5 Programming and Control
      1. 9.5.1 I2 C Serial Communication Bus
      2. 9.5.2 Slave Address
        1. 9.5.2.1 Random Write
        2. 9.5.2.2 Sequential Write
        3. 9.5.2.3 Random Read
        4. 9.5.2.4 Sequential Read
        5. 9.5.2.5 DSP Memory Book, Page and BQ update
        6. 9.5.2.6 Example Use
        7. 9.5.2.7 Checksum
          1. 9.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum
          2. 9.5.2.7.2 Exclusive or (XOR) Checksum
      3. 9.5.3 Control via Software
        1. 9.5.3.1 Startup Procedures
        2. 9.5.3.2 Shutdown Procedures
        3. 9.5.3.3 Protection and Monitoring
          1. 9.5.3.3.1 Overcurrent Shutdown (OCSD)
          2. 9.5.3.3.2 DC Detect
    6. 9.6 Register Maps
      1. 9.6.1 CONTROL PORT Registers
        1. 9.6.1.1  RESET_CTRL Register (Offset = 1h) [reset = 0x00]
          1. Table 7. RESET_CTRL Register Field Descriptions
        2. 9.6.1.2  DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
          1. Table 8. DEVICE_CTRL_1 Register Field Descriptions
        3. 9.6.1.3  DEVICE_CTRL_2 Register (Offset = 3h) [reset = 0x10]
          1. Table 9. DEVICE_CTRL_2 Register Field Descriptions
        4. 9.6.1.4  I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
          1. Table 10. I2C_PAGE_AUTO_INC Register Field Descriptions
        5. 9.6.1.5  SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
          1. Table 11. SIG_CH_CTRL Register Field Descriptions
        6. 9.6.1.6  CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
          1. Table 12. CLOCK_DET_CTRL Register Field Descriptions
        7. 9.6.1.7  SDOUT_SEL Register (Offset = 30h) [reset = 0h]
          1. Table 13. SDOUT_SEL Register Field Descriptions
        8. 9.6.1.8  I2S_CTRL Register (Offset = 31h) [reset = 0x00]
          1. Table 14. I2S_CTRL Register Field Descriptions
        9. 9.6.1.9  SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
          1. Table 15. SAP_CTRL1 Register Field Descriptions
        10. 9.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
          1. Table 16. SAP_CTRL2 Register Field Descriptions
        11. 9.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]
          1. Table 17. SAP_CTRL3 Register Field Descriptions
        12. 9.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]
          1. Table 18. FS_MON Register Field Descriptions
        13. 9.6.1.13 BCK_MON Register (Offset = 38h) [reset = 0x00]
          1. Table 19. BCK_MON Register Field Descriptions
        14. 9.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
          1. Table 20. CLKDET_STATUS Register Field Descriptions
        15. 9.6.1.15 CHANNEL_FORCE_HIZ Register (Offset = 40h) [reset = 0x01]
          1. Table 21. CHANNEL_FORCE_HIZ Register Field Descriptions
        16. 9.6.1.16 DIG_VOL_CTL Register (Offset = 4Ch) [reset = 30h]
          1. Table 22. DIG_VOL_CTR Register Field Descriptions
        17. 9.6.1.17 DIG_VOL_CTRL2 Register (Offset = 4Eh) [reset = 0x33]
          1. Table 23. DIG_VOL_CTRL2 Register Field Descriptions
        18. 9.6.1.18 DIG_VOL_CTRL3 Register (Offset = 4Fh) [reset = 0x30]
          1. Table 24. DIG_VOL_CTRL3 Register Field Descriptions
        19. 9.6.1.19 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
          1. Table 25. AUTO_MUTE_CTRL Register Field Descriptions
        20. 9.6.1.20 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
          1. Table 26. AUTO_MUTE_TIME Register Field Descriptions
        21. 9.6.1.21 ANA_CTRL Register (Offset = 53h) [reset = 0x00]
          1. Table 27. ANA_CTRL Register Field Descriptions
        22. 9.6.1.22 AGAIN Register (Offset = 54h) [reset = 0x00]
          1. Table 28. AGAIN Register Field Descriptions
        23. 9.6.1.23 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]
          1. Table 29. BQ_WR_CTRL1 Register Field Descriptions
        24. 9.6.1.24 DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]
          1. Table 30. DAC_CTRL Register Field Descriptions
        25. 9.6.1.25 ADR_PIN_CTRL Register (Offset = 60h) [reset = 0h]
          1. Table 31. ADR_PIN_CTRL Register Field Descriptions
        26. 9.6.1.26 ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]
          1. Table 32. ADR_PIN_CONFIG Register Field Descriptions
        27. 9.6.1.27 DSP_MISC Register (Offset = 66h) [reset = 0h]
          1. Table 33. DSP_MISC Register Field Descriptions
        28. 9.6.1.28 DIE_ID Register (Offset = 67h) [reset = 0h]
          1. Table 34. DIE_ID Register Field Descriptions
        29. 9.6.1.29 POWER_STATE Register (Offset = 68h) [reset = 0x00]
          1. Table 35. POWER_STATE Register Field Descriptions
        30. 9.6.1.30 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
          1. Table 36. AUTOMUTE_STATE Register Field Descriptions
        31. 9.6.1.31 PHASE_CTRL Register (Offset = 6Ah) [reset = 0x00]
          1. Table 37. PHASE_CTR Register Field Descriptions
        32. 9.6.1.32 SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
          1. Table 38. SS_CTRL0 Register Field Descriptions
        33. 9.6.1.33 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
          1. Table 39. SS_CTRL1 Register Field Descriptions
        34. 9.6.1.34 SS_CTRL2 Register (Offset = 6Dh) [reset = 0x50]
          1. Table 40. SS_CTRL2 Register Field Descriptions
        35. 9.6.1.35 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
          1. Table 41. SS_CTRL3 Register Field Descriptions
        36. 9.6.1.36 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
          1. Table 42. SS_CTRL4 Register Field Descriptions
        37. 9.6.1.37 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
          1. Table 43. CHAN_FAULT Register Field Descriptions
        38. 9.6.1.38 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
          1. Table 44. GLOBAL_FAULT1 Register Field Descriptions
        39. 9.6.1.39 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
          1. Table 45. GLOBAL_FAULT2 Register Field Descriptions
        40. 9.6.1.40 OT WARNING Register (Offset = 73h) [reset = 0x00]
          1. Table 46. OT_WARNING Register Field Descriptions
        41. 9.6.1.41 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
          1. Table 47. PIN_CONTROL1 Register Field Descriptions
        42. 9.6.1.42 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
          1. Table 48. PIN_CONTROL2 Register Field Descriptions
        43. 9.6.1.43 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
          1. Table 49. MISC_CONTROL Register Field Descriptions
        44. 9.6.1.44 HP_CONTROL Register (Offset = 77h) [reset = 0x00]
          1. Table 50. HP_CONTROL Register Field Descriptions
        45. 9.6.1.45 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
          1. Table 51. FAULT_CLEAR Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Bootstrap Capacitors
      2. 10.1.2 Inductor Selections
      3. 10.1.3 Power Supply Decoupling
      4. 10.1.4 Output EMI Filtering
    2. 10.2 Typical Applications
      1. 10.2.1 2.0 (Stereo BTL) System
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design Procedure
        1. 10.2.3.1 Step 1: Hardware Integration
        2. 10.2.3.2 Step2: Speaker Tuning
        3. 10.2.3.3 Software Integration
      4. 10.2.4 Application Curves
      5. 10.2.5 Mono (PBTL) system
      6. 10.2.6 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 DVDD Supply
    2. 11.2 PVDD Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General Guidelines for Audio Amplifiers
      2. 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 12.1.3 Optimizing Thermal Performance
        1. 12.1.3.1 Device, Copper, and Component Layout
        2. 12.1.3.2 Stencil Pattern
          1. 12.1.3.2.1 PCB footprint and Via Arrangement
          2. 12.1.3.2.2 Solder Stencil
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
      2. 13.1.2 Development Support
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.1 Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5806MDEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency set to 1 kHz and device PWM Modulation mode set to 1 SPW mode with Class D Bandwidth =120 kHz for 576kHz Fsw and Class D Bandwidth = 175 kHz for 768 kHz Fsw (Listed in Register 0x53) unless otherwise noted.

TAS5806MD D102.gif
PVDD = 5 V 4.7 µH + 0.68 µF
FSW = 576 kHz 1 SPW Modulation Load = 4 Ω
Figure 1. THD+N vs Frequency-BTL
TAS5806MD D109.gif
PVDD = 12 V 4.7 µH + 0.68 µF
FSW = 768 kHz 1SPW Modulation Load = 4 Ω
Figure 3. THD+N vs Frequency-BTL
TAS5806MD D104.gif
PVDD = 18 V 10 µH + 0.68 µF
FSW = 768 kHz 1SPW Modulation Load = 6 Ω
Figure 5. THD+N vs Frequency-BTL
TAS5806MD D106.gif
PVDD = 12 V 4.7 µH + 0.68 µF
FSW = 768 kHz 1SPW Modulation Load = 8 Ω
Figure 7. THD+N vs Frequency-BTL
TAS5806MD D108.gif
PVDD = 24 V 10 µH + 0.68 µF
FSW = 768 kHz 1SPW Modulation Load = 8 Ω
Figure 9. THD+N vs Frequency-BTL
TAS5806MD D112.gif
1.
PVDD = 5 V 1SPW Modulation 4.7 µH + 0.68 µF
FSW = 768 kHz Load = 4 Ω
Figure 11. THD+N vs Output Power-BTL
TAS5806MD D114.gif
1.
PVDD = 12 V 1SPW Modulation 4.7 µH + 0.68 µF
FSW = 768 kHz Load = 6 Ω
Figure 13. THD+N vs Output Power-BTL
TAS5806MD D116.gif
1.
PVDD = 24 V 1SPW Modulation 10 µH + 0.68 µF
FSW = 768 kHz Load = 6 Ω
Figure 15. THD+N vs Output Power-BTL
TAS5806MD D118.gif
1.
PVDD = 18 V 1SPW Modulation 10 µH + 0.68 µF
FSW = 768 kHz Load = 8 Ω
Figure 17. THD+N vs Output Power-BTL
TAS5806MD D120.gif
1. Dashed lines represent thermally limited region for the continuous output power.
PVDD = 4.5V~16V 1SPW Modulation 4.7 µH + 0.68 µF
FSW = 768 kHz Load = 4 Ω
Figure 19. Output Power vs Supply Voltage
TAS5806MD D122.gif
1. Dashed lines represent thermally limited region for the continuous output power.
PVDD = 4.5V~24V 1SPW Modulation 10 µH + 0.68 µF
FSW = 768 kHz Load = 8 Ω
Figure 21. Output Power vs Supply Voltage
TAS5806MD 900.gif
1.
PVDD = 7.4 V, 12 V, 18 V, 24 V 10 µH + 0.68 µF
FSW = 768 kHz Load = 6 Ω 1 SPW Modulation
Figure 23. Efficiency vs Supply Voltage
TAS5806MD D126.gif
1.
PVDD = 4.5V~24V 1 SPW Modulation 10 µH + 0.68 µF
FSW = 768 kHz Load = 8 Ω
Figure 25. Idle Channel Noise vs Supply Voltage
TAS5806MD D129.gif
1.
PVDD = 18 V 1 SPW Modulation 10 µH + 0.68 µF
FSW = 768 kHz Load = 6 Ω PO = 1 W
Figure 27. Crosstalk
TAS5806MD D131.gif
1.
PVDD = 12 V 1 SPW Modulation 4.7 µH + 0.68 µF
FSW = 768 kHz Load = 8 Ω PO = 1 W
Figure 29. Crosstalk
TAS5806MD D133.gif
1.
PVDD = 24 V 1 SPW Modulation 10 µH + 0.68 µF
FSW = 768 kHz Load = 8 Ω PO = 1 W
Figure 31. Crosstalk
TAS5806MD D101.gif
PVDD = 7.4 V 4.7 µH + 0.68 µF
FSW = 576 kHz 1SPW Modulation Load = 4 Ω
Figure 2. THD+N vs Frequency-BTL
TAS5806MD D103.gif
PVDD = 12 V 4.7 µH + 0.68 µF
FSW = 768 kHz 1SPW Modulation Load = 6 Ω
Figure 4. THD+N vs Frequency-BTL
TAS5806MD D105.gif
PVDD = 24 V 10 µH + 0.68 µF
FSW = 768 kHz 1SPW Modulation Load = 6 Ω
Figure 6. THD+N vs Frequency-BTL
TAS5806MD D107.gif
PVDD = 18 V 10 µH + 0.68 µF
FSW = 768 kHz 1SPW Modulation Load = 8 Ω
Figure 8. THD+N vs Frequency-BTL
TAS5806MD D110.gif
1.
PVDD = 19 V Hybrid, BD PO = 5 W
FSW = 384 kHz 1 SPW Modulation Load = 6 Ω
Figure 10. THD+N vs Frequency-BTL
TAS5806MD D113.gif
1.
PVDD = 12 V 1SPW Modulation 4.7 µH + 0.68 µF
FSW = 768 kHz Load = 4 Ω
Figure 12. THD+N vs Output Power-BTL
TAS5806MD D115.gif
1.
PVDD = 18 V 1SPW Modulation 10 µH + 0.68 µF
FSW = 768 kHz Load = 6 Ω
Figure 14. THD+N vs Output Power-BTL
TAS5806MD D117.gif
1.
PVDD = 12 V 1SPW Modulation 10 µH + 0.68 µF
FSW = 768 kHz Load = 8 Ω
Figure 16. THD+N vs Output Power-BTL
TAS5806MD D119.gif
1.
PVDD = 24 V 1SPW Modulation 10 µH + 0.68 µF
FSW = 768 kHz Load = 8 Ω
Figure 18. THD+N vs Output Power-BTL
TAS5806MD D121.gif
1. Dashed lines represent thermally limited region for the continuous output power.
PVDD = 4.5V~24V 1SPW Modulation 10 µH + 0.68 µF
FSW = 768 kHz Load = 6 Ω
Figure 20. Output Power vs Supply Voltage
TAS5806MD D123.gif
1.
PVDD = 4.5 V, 7.4 V, 12 V 1 SPW Modulation
FSW = 768 kHz Load = 4 Ω 4.7 µH + 0.68 µF
Figure 22. Efficiency vs Supply Voltage
TAS5806MD 901.gif
1.
PVDD = 7.4 V, 12 V, 18 V, 24 V 10 µH + 0.68 µF
FSW = 768 kHz Load = 8 Ω 1SPW Modulation
Figure 24. Efficiency vs Supply Voltage
TAS5806MD D128.gif
1.
PVDD = 12 V 1 SPW Modulation 4.7 µH + 0.68 µF
FSW = 768 kHz Load = 6 Ω PO = 1 W
Figure 26. Crosstalk
TAS5806MD D130.gif
1.
PVDD = 24 V 1 SPW Modulation 10 µH + 0.68 µF
FSW = 768 kHz Load = 6 Ω PO = 1 W
Figure 28. Crosstalk
TAS5806MD D132.gif
1.
PVDD = 18 V 1 SPW Modulation 10 µH + 0.68 µF
FSW = 768 kHz Load = 8 Ω PO = 1 W
Figure 30. Crosstalk