9.6.1.24 DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]
DAC_CTRL is shown in Figure 105 and described in Table 30.
Return to Summary Table.
Figure 105. DAC_CTRL Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
DAC_FREQUENCY_SEL |
DAC_DITHER_EN |
DAC_DITHER |
DAC_CTRL_DEM_SEL |
R/W |
R/W |
R/W |
R/W |
|
Table 30. DAC_CTRL Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
DAC_FREQUENCY_SEL |
R/W |
1 |
DAC Frequency Select
0: 6.144MHz
1: 3.072MHz
|
6-5 |
DAC_DITHER_EN |
R/W |
11 |
DITHER_EN,
00: disable both stage dither
01: enable main stage dither
10: enable second stage dither
11: enbale both stage dither |
4-2 |
DAC_DITHER |
R/W |
110 |
Dither level
100: -2^-7
101: -2^-8
110: -2^-9
111: -2^-10
000: -2^-13
001: -2^-14
010: -2^-15
011: -2^-16 |
1-0 |
DAC_CTRL_DEM_SEL |
R/W |
00 |
00: Enable DEM
11: Disable DEM
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