9.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
DEVICE_CTRL_1 is shown in Figure 83 and described in Table 8.
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Figure 83. DEVICE_CTRL_1 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
FSW_SEL |
RESERVED |
DAMP_PBTL |
DAMP_MOD |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Table 8. DEVICE_CTRL_1 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
RESERVED |
R/W |
0 |
This bit is reserved
|
6-4 |
FSW_SEL |
R/W |
000 |
SELECT FSW
000:768K
001:384K
011:480K
100:576K
010:Reserved
101:Reserved
110:Reserved
111:Reserved |
3 |
RESERVED |
R/W |
0 |
This bit is reserved
|
2 |
DAMP_PBTL |
R/W |
0 |
0: SET DAMP TO BTL MODE
1: SET DAMP TO PBTL MODE |
1-0 |
DAMP_MOD |
R/W |
00 |
00:BD MODE
01:1SPW MODE
10:HYBRID MODE
|